Datasheet

1Z1P
)
,min( Z
Z
5
x
0U
T
2P
=
Z
=
0U
T
=
SNSCSH
RR500VD
xxx
c
620VD x
c
( )
LIM
LED
RID1 xx+
( )
LIMHSP
RRD1
xx+
=
0U
T
=
SNSCSH
RR500VD
xxx
c
310VD
x
c
LIMLED
RI
x
LIMHSP
RR2
xx
SNS
620V
RR500V
=
xx
CSH
LIMLED
RI
x
0U
T
=
LIMHSP
RR
x
=
Dr
2
D
c
x
1Z
Z
L1Dx
=
Dr
2
D
c
x
1Z
Z
L1
1P
=Z
1+D
OD
Cr x
3
1P
=Z
2
OD
Cr x
3
1P
=Z
1
OD
Cr x
3
x
=
¨
¨
©
§
+
s
1
Z
1P
¸
¸
¹
·
0U
T
U
T
¨
¨
©
§
-
s
1
Z
1Z
¸
¸
¹
·
LM3429, LM3429-Q1
www.ti.com SNVS616G –APRIL 2009–REVISED MAY 2013
Boost and Buck-boost
(47)
Where the pole (ω
P1
) is approximated:
Buck
(48)
Boost
(49)
Buck-boost
(50)
And the RHP zero (ω
Z1
) is approximated:
Boost
(51)
Buck-boost
(52)
And the uncompensated DC loop gain (T
U0
) is approximated:
Buck
(53)
Boost
(54)
Buck-boost
(55)
For all topologies, the primary method of compensation is to place a low frequency dominant pole (ω
P2
) which
will ensure that there is ample phase margin at the crossover frequency. This is accomplished by placing a
capacitor (C
CMP
) from the COMP pin to GND, which is calculated according to the lower value of the pole and the
RHP zero of the system (shown as a minimizing function):
(56)
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: LM3429 LM3429-Q1