Datasheet
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
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ELECTRICAL CHARACTERISTICS
(1)
(continued)
Specifications in standard type face are for T
J
= 25°C and those with boldface type apply over the full Operating
Temperature Range ( T
J
= −40°C to +125°C). Minimum and Maximum limits are specified through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at T
J
= +25°C, and are provided for reference purposes
only. Unless otherwise stated the following condition applies: V
IN
= +14V.
Min Typ Max
Symbol Parameter Conditions Units
(2) (3) (2)
THERMAL SHUTDOWN
T
SD
Thermal Shutdown
(6)
165
Threshold
°C
T
HYS
Thermal Shutdown
(6)
25
Hysteresis
THERMAL RESISTANCE
θ
JA
Junction to Ambient 20L HTSSOP EP
(7)
34 °C/W
(6) These electrical parameters are specified by design, and are not verified by test.
(7) Junction-to-ambient thermal resistance is highly board-layout dependent. The numbers listed in the table are given for a reference layout
wherein the 20L HTSSOP EP package has its DAP pad populated with 9 vias. In applications where high maximum power dissipation
exists, namely driving a large MosFET at high switching frequency from a high input voltage, special care must be paid to thermal
dissipation issues during board design. In high-power dissipation applications, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T
A-MAX
) is dependent on the maximum operating junction temperature (T
J-MAX-OP
= 125°C), the
maximum power dissipation of the device in the application (P
D-MAX
), and the junction-to ambient thermal resistance of the package in
the application (θ
JA
), as given by the following equation: T
A-MAX
= T
J-MAX-OP
– (θ
JA
× P
D-MAX
). In most applications there is little need for
the full power dissipation capability of this advanced package. Under these circumstances, no vias would be required and the thermal
resistances would be 104 °C/W for the 20L HTSSOP EP. It is possible to conservatively interpolate between the full via count thermal
resistance and the no via count thermal resistance with a straight line to get a thermal resistance for any number of vias in between
these two limits.
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