Datasheet
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
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PIN DESCRIPTIONS (continued)
Pin Name Description Application Information
Connect to gate of main switching
15 GATE Main Gate Drive Output
MosFET.
Bypass with a 2.2 µF – 3.3 µF,
16 V
CC
Internal Regulator Output
ceramic capacitor to GND.
Connect to the drain of the main N-
channel MosFET switch for R
DS-ON
17 IS Main Switch Current Sense sensing or to a sense resistor
installed in the source of the same
device.
Connect a resistor to GND to set
18 SLOPE Slope Compensation
slope of additional ramp.
Connect through a series resistor to
19 HSN LED Current Sense Negative LED current sense resistor
(negative).
Connect through a series resistor to
20 HSP LED Current Sense Positive
LED current sense resistor (positive).
Connect to GND. Refer to
(1)
for
DAP DAP Thermal pad on bottom of IC
thermal considerations.
(1) Junction-to-ambient thermal resistance is highly board-layout dependent. The numbers listed in the table are given for a reference layout
wherein the 20L HTSSOP EP package has its DAP pad populated with 9 vias. In applications where high maximum power dissipation
exists, namely driving a large MosFET at high switching frequency from a high input voltage, special care must be paid to thermal
dissipation issues during board design. In high-power dissipation applications, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T
A-MAX
) is dependent on the maximum operating junction temperature (T
J-MAX-OP
= 125°C), the
maximum power dissipation of the device in the application (P
D-MAX
), and the junction-to ambient thermal resistance of the package in
the application (θ
JA
), as given by the following equation: T
A-MAX
= T
J-MAX-OP
– (θ
JA
× P
D-MAX
). In most applications there is little need for
the full power dissipation capability of this advanced package. Under these circumstances, no vias would be required and the thermal
resistances would be 104 °C/W for the 20L HTSSOP EP. It is possible to conservatively interpolate between the full via count thermal
resistance and the no via count thermal resistance with a straight line to get a thermal resistance for any number of vias in between
these two limits.
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