Datasheet

1
=
C
FS
3P
10
x
Z
max
3P
=
Z
( )
10,
1Z1P
x
ZZ
1
CMP
C
=
6
2P
e5
x
Z
1Z1P
)
,min( Z
Z
5
x
0U
T
2P
=
Z
=
0U
T
=
SNSCSH
RR500VD
xxx
c
620VD
x
c
( )
LIM
LED
RID1
xx+
( )
LIMHSP
RRD1 xx+
=
0U
T
=
SNSCSH
RR500VD
xxx
c
310VD
x
c
LIMLED
RI x
LIMHSP
RR2 xx
SNS
620V
RR500V
=
xx
CSH
LIMLED
RI
x
0U
T
=
LIMHSP
RR
x
=
Dr
2
D
c
x
1Z
Z
L1Dx
=
Dr
2
D
c
x
1Z
Z
L1
1P
=Z
1+D
OD
Cr x
3
1P
=Z
2
OD
Cr x
3
1P
=Z
1
OD
Cr x
3
LM3424
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009 www.ti.com
Where the pole (ω
P1
) is approximated:
Buck
(58)
Boost
(59)
Buck-boost
(60)
And the RHP zero (ω
Z1
) is approximated:
Boost
(61)
Buck-boost
(62)
And the uncompensated DC loop gain (T
U0
) is approximated:
Buck
(63)
Boost
(64)
Buck-boost
(65)
For all topologies, the primary method of compensation is to place a low frequency dominant pole (ω
P2
) which
will ensure that there is ample phase margin at the crossover frequency. This is accomplished by placing a
capacitor (C
CMP
) from the COMP pin to GND, which is calculated according to the lower value of the pole and the
RHP zero of the system (shown as a minimizing function):
(66)
(67)
If analog dimming is used, C
CMP
should be approximately 4x larger to maintain stability as the LEDs are dimmed
to zero.
A high frequency compensation pole (ω
P3
) can be used to attenuate switching noise and provide better gain
margin. Assuming R
FS
= 10Ω, C
FS
is calculated according to the higher value of the pole and the RHP zero of
the system (shown as a maximizing function):
(68)
(69)
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