Datasheet
V
CMP
0
t
VCC
t
CMP
t
CO
t
0
t
VCC
t
CMP-SS
t
CO
0.9V
t
SS
0.9V
0.7V
PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
80
60
40
20
0
-20
-40
-60
-80
90
45
0
-45
-90
-135
-180
-225
-270
1e-1 1e1 1e3 1e5 1e7
GAIN
60° Phase Margin
PHASE
ö
P2
ö
P3
ö
P1
ö
Z1
x=
0U
TT
-1
¸
¸
¹
·
¨
¨
©
§
s
Z
1
Z
xx +1
¸
¸
¹
·
¨
¨
©
§
s
Z
3P
+1
¸
¸
¹
·
¨
¨
©
§
s
Z
2P
+1
¸
¸
¹
·
¨
¨
©
§
s
Z
1P
1
3P
=Z
FSFS
CR x
1
2P
=Z
CMP
6
Ce5 x
:
LM3424
www.ti.com
SNVS603B –AUGUST 2009–REVISED OCTOBER 2009
The dominant compensation pole (ω
P2
) is determined by C
CMP
and the output resistance (R
O
) of the error
amplifier (typically 5 MΩ):
(19)
It may also be necessary to add one final pole at least one decade above the crossover frequency to attenuate
switching noise and, in some cases, provide better gain margin. This pole can be placed across R
SNS
to filter the
ESL of the sense resistor at the same time. Figure 28 shows how the compensation is physically implemented in
the system.
The high frequency pole (ω
P3
) can be calculated:
(20)
The total system transfer function becomes:
(21)
The resulting compensated loop gain frequency response shown in Figure 29 indicates that the system has
adequate phase margin (above 45°) if the dominant compensation pole is placed low enough, ensuring stability:
Figure 29. Compensated Loop Gain Frequency Response
Figure 30. Start-up Waveforms
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