Datasheet

1Z1P
)
,min( Z
Z
5
x
0U
T
2P
=
Z
=
0U
T
=
SNSCSH
RR500VD
xxx
c
620VD
x
c
( )
LIM
LED
RID1
xx+
( )
LIMHSP
RRD1
xx+
=
0U
T
=
SNSCSH
RR500VD
xxx
c
310VD
x
c
LIMLED
RI
x
LIMHSP
RR2
xx
SNS
620V
RR500V
=
xx
CSH
LIMLED
RI
x
0U
T
=
LIMHSP
RR
x
=
Dr
2
D
c
x
1Z
Z
L1Dx
=
Dr
2
D
c
x
1Z
Z
L1
1P
=Z
1+D
OD
Cr x
3
1P
=Z
2
OD
Cr x
3
1P
=Z
1
OD
Cr x
3
x
=
¨
¨
©
§
+
s
1
Z
1P
¸
¸
¹
·
0U
T
U
T
¨
¨
©
§
-
s
1
Z
1Z
¸
¸
¹
·
LM3421, LM3421-Q1
LM3423, LM3423-Q1
SNVS574E –JULY 2008–REVISED MAY 2013 www.ti.com
Boost and Buck-boost
(54)
Where the pole (ω
P1
) is approximated:
Buck
(55)
Boost
(56)
Buck-boost
(57)
And the RHP zero (ω
Z1
) is approximated:
Boost
(58)
Buck-boost
(59)
And the uncompensated DC loop gain (T
U0
) is approximated:
Buck
(60)
Boost
(61)
Buck-boost
(62)
For all topologies, the primary method of compensation is to place a low frequency dominant pole (ω
P2
) which
will ensure that there is ample phase margin at the crossover frequency. This is accomplished by placing a
capacitor (C
CMP
) from the COMP pin to AGND, which is calculated according to the lower value of the pole and
the RHP zero of the system (shown as a minimizing function):
(63)
34 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
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