Datasheet
LM3421/23
R
UV2
R
UV1
V
IN
nDIM
R
UVH
Q
DIM
D
DIM
Inverted
PWM
Standard
PWM
x
PA23
=
HYS
V
¨
¨
©
§
+
2UV
R
¸
¸
¹
·
1UV
R
(
+
x
1UV
R
)
2UV
R
UVH
R
2UV
RA23
x
P
HYS
V
=
1
¸
¸
¹
·
¨
¨
©
§
x
=
-ONTURN
24V.1V
1UV
R
+
2UVUV
RR
LM3421, LM3421-Q1
LM3423, LM3423-Q1
www.ti.com
SNVS574E –JULY 2008–REVISED MAY 2013
(29)
The hysteresis (V
HYS
) is defined as follows:
UVLO only
(30)
PWM dimming and UVLO
(31)
When "zero current" shutdown and UVLO are implemented together, the EN pin can be used to escape UVLO.
The nDIM pin will pull-up to V
IN
when EN is pulled low, therefore if V
IN
is within the UVLO hysteretic window
when EN is pulled high again, the controller will start-up even though V
TURN-ON
is not exceeded.
PWM DIMMING
The active low nDIM pin can be driven with a PWM signal which controls the main NFET and the dimming FET
(dimFET). The brightness of the LEDs can be varied by modulating the duty cycle of this signal. LED brightness
is approximately proportional to the PWM signal duty cycle, (i.e. 30% duty cycle ~ 30% LED brightness). This
function can be ignored if PWM dimming is not required by using nDIM solely as a V
IN
UVLO input as described
in the INPUT UNDER-VOLTAGE LOCKOUT (UVLO) section or by tying it directly to V
CC
or V
IN
.
Figure 29. PWM Dimming Circuit
Figure 29 shows how the PWM signal is applied to nDIM:
1. Connect the dimming MosFET (Q
DIM
) with the drain to the nDIM pin and the source to AGND. Apply an
external logic-level PWM signal to the gate of Q
DIM
.
2. Connect the anode of a Schottky diode (D
DIM
) to the nDIM pin. Apply an inverted external logic-level PWM
signal to the cathode of the same diode.
The DDRV pin is a PWM output that follows the nDIM PWM input signal. When the nDIM pin rises, the DDRV pin
rises and the PWM latch reset signal is removed allowing the main MosFET Q1 to turn on at the beginning of the
next clock set pulse. In boost and buck-boost topologies, the DDRV pin is used to control a N-channel MosFET
placed in series with the LED load, while it would control a P-channel MosFET in parallel with the load for a buck
topology.
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