Datasheet

UVLO
1
VCC
2
VIN
3
4
12
EN
11
IADJ
10
CSP
5
13
14
COFF CSN
NC
NC
6
GND
9
8
PGATE
7
NC NC
UVLO
1
CSP
2
VIN
3
4
8
COFF
7
EN
6
CSN
5
9
10
GND PGATE
DAP
VCC
IADJ
LM3409, LM3409HV, LM3409-Q1
SNVS602J –MARCH 2009–REVISED MAY 2013 www.ti.com
Connection Diagram
LM3409/09Q/09HV/09QHV LM3409N
Figure 1. 10-Lead VSSOP Package Figure 2. 14-Lead PDIP Package
PIN DESCRIPTIONS
Pins
Name Description Application Information
PDIP VSSOP
1 1 UVLO Input under-voltage lockout Connect to a resistor divider from V
IN
and GND. Turn-on
threshold is 1.24V and hysteresis for turn-off is provided by a
22µA current source.
3 2 IADJ Analog LED current adjust Apply a voltage between 0 - 1.24V, connect a resistor to GND, or
leave open to set the current sense threshold voltage.
4 3 EN Logic level enable / Apply a voltage >1.74V to enable device, a PWM signal to dim, or
PWM dimming a voltage <0.5V for low power shutdown.
5 4 COFF Off-time programming Connect resistor from V
O
, capacitor to GND to set off-time.
6 5 GND Ground Connect to system ground.
9 6 PGATE Gate drive Connect to gate of external PFET.
10 7 CSN Negative current sense Connect to negative side of sense resistor.
11 8 CSP Positive current sense Connect to positive side of sense resistor (also to VIN).
12 9 VCC V
IN
- referenced Connect at least a 1µF ceramic capacitor to V
IN
. The regulator
linear regulator output provides power for the PFET drive.
14 10 VIN Input voltage Connect to the input voltage.
DAP DAP Thermal pad on bottom of IC Connect to GND pin. Place 4-6 vias from DAP to GND plane.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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