Datasheet
LM3370
www.ti.com
SNVS406N –NOVEMBER 2005–REVISED MAY 2013
Thermal Properties
(1)
Junction-to-Ambient Thermal Resistance
θ
JA
(WSON-16) 26°C/W
θ
JA
(20-Bump DSBGA) 50°C/W
(1) Junction-to-ambient thermal resistance (θ
JA
) is taken from a thermal modeling result, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2 x 1 array
of thermal vias. Thickness of copper layers are 2/1/1/2oz. Junction-to-ambient thermal resistance is highly application and board-layout
dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in
board design.The value of θ
JA
of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In
applications where high maximum power dissipation exists (high V
IN
, high I
OUT
), special care must be paid to thermal dissipation issues.
For more information on these topics, please refer to Application Note 1187: Leadless Leadframe Package (LLP) (SNOA401).
Electrical Characteristics
(1)(2)(3)
Typical limits appearing in normal type apply for T
J
= 25°C. Limits appearing in boldface type apply over the entire junction
temperature range (T
A
= T
J
= −30°C to +85°C). Unless otherwise noted, V
IN1
= V
IN2
= 3.6V.
Symbol Parameter Conditions Min Typ Max Units
V
FB
Feedback Voltage
(4)
−3.5 +3.5 %
V
OUT
Line Regulation 2.7V ≤ V
IN
≤ 5.5V 0.031 %/V
I
O
= 10 mA, V
OUT
= 1.8V
Load Regulation 100 mA ≤ I
O
≤ 600 mA 0.0013 %/mA
V
IN
= 3.6V, V
OUT
= 1.8V
I
Q
PFM Quiescent Current “On” PFM Mode, Both Bucks ON 34 µA
I
Q
SD Quiescent Current “Off” EN1 = EN2 = 0V 0.2 3 µA
I
LIM
Peak Switching Current Limit V
IN
= 3.6V 850 1200 1400 mA
R
DS_ON
PFET V
IN
= 3.6V, I
SW
= 200 mA 390 500
mΩ
(WSON)
NFET V
IN
= 3.6V, I
SW
= 200 mA 240 350
R
DS_ON
PFET V
IN
= 3.6V, I
SW
= 200 mA 350 400
mΩ
(DSBGA)
NFET V
IN
= 3.6V, I
SW
= 200 mA 170 210
F
OSC
Internal Oscillator Frequency 1.5 2.0 2.4 MHz
I
EN
Enable (EN) Input Current 0.01 1 µA
V
IL
Enable Logic Low 0.4 V
V
IH
Enable Logic High 1.0 V
POWER ON RESET THRESHOLD/FUNCTION (POR)
nPOR1 and nPOR1 = Power ON Reset 50 mS (default)
nPOR2 for Buck 1
50 mS
Delay Time
nPOR2 = Power ON Reset Can be pre-trimmd to 50 uS, 100
for Buck 2 mS and 200 mS
POR Percentage of Target V
OUT
V
OUT
Rising 94
Threshold
%
V
OUT
Falling, 85% (default), Can be 85
pre-trimmed to 70% or 94%
(1) All voltages are with respect to the potential at the GND pin.
(2) Min. and Max are specified by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are
tested during production with T
J
= 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
(3) Input voltage range for all voltage options is 2.7V to 5.5V. The voltage range recommended for the specified output voltages: V
IN
= 2.7V
to 5.5V for 1V ≤ V
OUT
≤ 1.7V and for V
OUT
= 1.8V or greater, V
IN
= V
OUT
+ 1VorV
IN,MIN
= I
LOAD
* (R
DSON_PFET
+ R
DCR_INDUCTOR
) + V
OUT
(4) Test condition: for V
OUT
less than 2.5V, V
IN
= 3.6V; for V
OUT
greater than or equal to 2.5V, V
IN
= V
OUT
+ 1V.
Dissipation Rating Table
θ
JA
T
A
= 60°C T
A
= 85°C
Power Rating Power Rating
26°C/W (4-Layer Board) WSON-16 1538 mW
50°C/W (4-Layer Board) 20-bump DSBGA 1300 mW 800 mW
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LM3370