Datasheet

B4B3
PGND1_S
C4C3C2
D4D2
SW1
A1
B1
C1
D1
E4E3E2
E1
B2
A2
A3
A4
VIN1
SGND
FB1
PGND1
SDA
SCL
VDD
SGND NPOR1
NPOR2
PGND2 PGND2_S EN2 EN1
SW2 VIN2 SGND
FB2
A
B
C
D
E
1
2 3 4
D3
B4 B3
PGND1_S
C4 C3 C2
D4 D2
SW1
A1
B1
C1
D1
E4 E3 E2
E1
B2
A2
A3
A4
VIN1
SGND
FB1
PGND1
SDA
SCL
VDD
SGNDNPOR1
NPOR2
PGND2PGND2_SEN2EN1
SW2VIN2SGND
FB2
A
B
C
D
E
1
234
D3
Bottom View
Top View
LM3370
SNVS406N NOVEMBER 2005REVISED MAY 2013
www.ti.com
Figure 2. DSBGA Connection Diagram
(See Package Number YZR0020DWA)
PIN DESCRIPTIONS (DSBGA)
Pin # Name Description
A1 SW1 Buck 1 Switch Pin
A2 V
IN1
Power supply voltage input to PFET and NFET switches for Buck 1
A3 SGND Signal GND
A4 FB1 Analog Feedback Input for Buck 1
B1 PGND1 Buck 1 Power Ground
B2 PGND1_S Buck 1 Power Ground Sense
B3 SDA I
2
C-Compatible Data, a 2 k pullup resistor is required
B4 SCL I
2
C-Compatible Clock, a 2 k pullup resistor is required
C1 V
DD
Signal supply voltage input, V
DD
must be equal or greater of the two inputs ( V
IN1
and V
IN2
)
C2 SGND Signal GND
Power ON Reset for Buck 1, Open drain output Low when Buck 1 output is 92% of target output.
C3 nPOR1
A 100 k pullup resistor is required
Power ON Reset for Buck 2, Open drain output Low when Buck 2 output is 92% of target output.
C4 nPOR2
A 100 k pullup resistor is required
D1 PGND2 Buck 2 Power Ground
D2 PGND2_S Buck 2 Power Ground Sense
D3 EN2 Buck 2 Enable
D4 EN1 Buck 1 Enable
E1 SW2 Buck 2 Switch Pin
E2 V
IN2
Power supply voltage input to PFET and NFET switches for Buck 2
E3 SGND Signal GND
E4 FB2 Analog feedback for Buck 2
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