Datasheet
SCL
SDA
S P
START condition STOP condition
SCL
SDA
data
change
allowed
data
change
allowed
data
change
allowed
data valid data valid
LM3370
www.ti.com
SNVS406N –NOVEMBER 2005–REVISED MAY 2013
Figure 37.
I
2
C-Compatible START and STOP Conditions
START and STOP bits classify the beginning and the end of the I
2
C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while SCL is HIGH. The I
2
C master always generates START and STOP bits.
The I
2
C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I
2
C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
Figure 38.
Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
The number of bytes that can be transmitted per transfer is unrestricted. Each byte of data has to be followed by
an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the
9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an
acknowledge after each byte has been received.
After the START condition, I
2
C master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). For the eighth bit, a “0” indicates a WRITE and a “1” indicates a
READ. The second byte selects the register to which the data will be written. The third byte contains data to write
to the selected register.
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