Datasheet
High PFM Threshold
~1.016*Vout
Low1 PFM Threshold
~1.008*Vout
PFM Mode at Light Load
PWM Mode at
Moderate to Heavy
Loads
Pfet on
until
Ipfm limit
reached
Nfet on
drains
conductor
current
until
I inductor=0
High PFM
Voltage
Threshold
reached,
go into
sleep mode
Low PFM
Threshold,
turn on
PFET
Current load
increases,
draws Vout
towards
Low2 PFM
Threshold
Low2 PFM Threshold,
switch back to PWM mode
Load current
increases
Low2 PFM Threshold
Vout
Z-
Ax
is
Z
-
Axis
LM3370
SNVS406N –NOVEMBER 2005–REVISED MAY 2013
www.ti.com
Figure 36. Operation in PFM Mode and Transfer to PWM Mode
Table 1. I
2
C-Compatible Interface Electrical Specifications
(1)
Symbol Parameter Conditions Min Typ Max Units
F
CLK
Clock Frequency 400 kHz
t
BF
Bus-Free Time between Start and Stop
(2)
1.3 µS
t
HOLD
Hold Time Repeated Start Condition
(2)
0.6 µS
t
CLKLP
CLK Low Period
(2)
1.3 µS
t
CLKHP
CLK High Period
(2)
0.6 µS
t
SU
Set Up Time Repeated Start Condition
(2)
0.6 µS
t
DATAHLD
Data Hold Time
(2)
200 nS
t
CLKSU
Data Set Up Time
(2)
200 nS
T
SU
Set Up Time for Start Condition
(2)
0.6 µS
T
TRANS
Maximum Pulse Width of Spikes that Must be Suppressed
(2)
50 nS
by the Input Filter of Both DATA and CLK signals.
VDD_I
2
C I
2
C Logic High Level 1 V
IN
V
(1) Unless otherwise noted, V
BATT
= 2.7V to 5.5V. Typical values and limits appearing in normal type apply for T
J
= 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, −30°C to +125°C.
(2) Input voltage range for all voltage options is 2.7V to 5.5V. The voltage range recommended for the specified output voltages: V
IN
= 2.7V
to 5.5V for 1V ≤ V
OUT
≤ 1.7V and for V
OUT
= 1.8V or greater, V
IN
= V
OUT
+ 1VorV
IN,MIN
= I
LOAD
* (R
DSON_PFET
+ R
DCR_INDUCTOR
) + V
OUT
I
2
C-Compatible Interface
In I
2
C-compatible mode, the SCL pin is used for the I
2
C clock and the SDA pin is used for the I
2
C data. Both
these signals need a pull-up resistor according to I
2
C specification. The values of the pull-up resistor are
determined by the capacitance of the bus (typ. ∼1.8k). Signal timing specifications are according to the I
2
C bus
specification. Maximum frequency is 400 kHz.
I
2
C-Compatible Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when CLK is LOW.
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