Datasheet

Pdh = 0.396 + 0.278 = 0.674W
Pcond = I
out
2
x R
DS(ON)
x D
8.5
Vcc - Vth
+
6.8
Vth
1
2
x V
in
x I
out
x Q
gd
x f
s
x
Psw =
Pdh = Pcond + Psw
Pcond = 12
2
x 0.01 x 0.275 = 0.396W
8.5
6 ± 2.5
+
6.8
2.5
1
2
x 12 x 12 x 1.5 nC x 500 kHz x
Psw =
= 0.278W
LM3151, LM3152, LM3153
www.ti.com SNVS562G –SEPTEMBER 2008–REVISED MARCH 2011
Minimum output capacitance is:
C
Omin
= 70 / (f
S
2
x L)
C
Omin
= 70 / (500 kHz
2
x 1.65 µH) = 169 µF
The maximum ESR allowed to prevent over-voltage protection during normal operation is:
ESR
max
= (80 mV x L) / ET
ESR
max
= (80 mV x 1.65 µH) / 5.7 V µs
ESR
max
= 23 mΩ
The minimum ESR must meet both of the following criteria:
ESR
min
≥ (15 mV x L) / ET
ESR
min
≥ [ET / (V
IN
- V
OUT
)] / C
O
ESR
min
≥ (15 mV x 1.65 µH) / 5.7 V µs = 4.3 mΩ
ESR
min
≥ [5.7 V µs / (12 - 3.3)] / 169 µF = 3.9 mΩ
Based on the above criteria two 150 µF polymer aluminum capacitors with a ESR = 12 mΩ each for a effective
ESR in parallel of 6 mΩ was chosen from Panasonic. The part number is EEF-UE0J151P.
5. MOSFET Selection
The LM3151/2/3 are designed to drive N-channel MOSFETs. For a maximum input voltage of 24V we should
choose N-channel MOSFETs with a maximum drain-source voltage, V
DS
, greater than 1.2 x 24V = 28.8V. FETs
with maximum V
DS
of 30V will be the first option. The combined total gate charge Q
gtotal
of the high-side and low-
side FET should satisfy the following:
Q
gtotal
≤ I
VCCL
/ f
s
(4)
Q
gtotal
≤ 65 mA / 500 kHz (5)
Q
gtotal
≤ 130 n
where
• I
VCCL
is the minimum current limit of VCC over the temperature range, specified in the electrical characteristics
table
The MOSFET gate charge Q
g
is gathered from reading the V
GS
vs Q
g
curve of the MOSFET datasheet at the
V
GS
= 5V for the high-side, M1, MOSFET and V
GS
= 6V for the low-side, M2, MOSFET.
The Renesas MOSFET RJK0305DPB has a gate charge of 10 nC at V
GS
= 5V, and 12 nC at V
GS
= 6V. This
combined gate charge for a high-side, M1, and low-side, M2, MOSFET 12 nC + 10 nC = 22 nC is less than 130
nC calculated Q
gtotal
.
The calculated MOSFET power dissipation must be less than the max allowed power dissipation, Pdmax, as
specified in the MOSFET datasheet. An approximate calculation of the FET power dissipated Pd, of the high-side
and low-side FET is given by:
High-Side MOSFET
The max power dissipation of the RJK0305DPB is rated as 45W for a junction temperature that is 125°C higher
than the case temperature and a thermal resistance from the FET junction to case, θ
JC
, of 2.78°C/W.
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