Datasheet

LM2854
www.ti.com SNVS560C –MARCH 2008–REVISED APRIL 2013
1. Minimize area of switched current loops.
There are two loops where currents are switched at high di/dt slew rates in a buck regulator. The first loop
represents the path taken by AC current flowing during the high side PFET on time. This current flows from
the input capacitor to the regulator PVIN pins, through the high side FET to the regulator SW pin, filter
inductor, output capacitor and returning via the PCB ground plane to the input capacitor.
The second loop represents the path taken by AC current flowing during the low side NFET on time. This
current flows from the output capacitor ground to the regulator PGND pins, through the NFET to the inductor
and output capacitor. From an EMI reduction standpoint, it is imperative to minimize this loop area during PC
board layout by physically locating the input capacitor close to the LM2854. Specifically, it is advantageous to
place C
IN
as close as possible to the LM2854 PVIN and PGND pins. Grounding for both the input and output
capacitor should consist of a localized top side plane that connects to PGND and the exposed die attach pad
(DAP). The inductor should be placed close to the SW pin and output capacitor.
2. Minimize the copper area of the switch node.
The LM2854 has two SW pins optimally located on one side of the package. In general the SW pins should
be connected to the filter inductor on the top PCB layer. The inductor should be placed close to the SW pins
to minimize the copper area of the switch node.
3. Have a single point ground for all device analog grounds located under the DAP.
The ground connections for the Feedback, Soft-start, Enable and AVIN components should be routed to the
AGND pin of the device. The AGND pin should connect to PGND under the DAP. This prevents any
switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding
can result in degraded load regulation or erratic switching behavior.
4. Minimize trace length to the FB pin.
Since the feedback (FB) node is high impedance, the trace from the output voltage setpoint resistor divider to
FB pin should be as short as possible. This is most important as relatively high value resistors are used to
set the output voltage. The FB trace should be routed away from the SW pin and inductor to avoid noise
pickup from the SW pin. Both feedback resistors, R
FB1
and R
FB2
, and the compensation components, R
COMP
and C
COMP
, should be located close to the FB pin.
5. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing
so will correct for voltage drops and provide optimum output accuracy.
6. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the DAP to the ground plane on the bottom PCB layer. If the
PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner
layer heat-spreading ground planes. For best results use a 5 x 3 via array with minimum via diameter of 10
mils. Ensure enough copper area is used to keep the junction temperature below 125°C.
LM2854 Application Circuit Schematic and BOMs
This section provides several application solutions with an associated bill of materials. All bill of materials
reference the schematic below. The compensation for each solution was optimized to work over the full input
range. Many applications have a fixed input voltage rail. It is possible to modify the compensation to obtain a
faster transient response for a given input voltage operating point.
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