Datasheet

C
COMP
(pF) = D
L
O
(PH)C
O
(PF)
V
IN
(V)
f
loop
(kHz)
PVIN
AVIN
EN
AGND PGND
FB
SW
LM2854
V
OUT
SS
L
O
C
O
R
FB1
R
COMP
C
COMP
R
FB2
V
IN
+
-
+
-
Error
Amp
V
REF
PWM
Comp
Ramp
R
DCR
R
ESR
R
L
1
R
ESR
+ R
L
L
O
C
O
f
LC
=
2S
R
DCR
+ R
L
L
O
C
O
2S
1
f
ESR
=
1
2SR
ESR
C
O
#
LM2854
www.ti.com SNVS560C –MARCH 2008–REVISED APRIL 2013
COMPENSATION COMPONENT SELECTION
The power stage transfer function of a voltage mode buck converter has a complex double pole related to the LC
output filter and a left half plane zero due to the output capacitor ESR, denoted R
ESR
. The locations of these
singularities are given respectively by
(12)
where C
O
is the output capacitance value appropriately derated for applied voltage and operating temperature,
R
L
is the effective load resistance and R
DCR
is the series damping resistance associated with the inductor and
power switches.
The conventional compensation strategy employed with voltage mode control is to use two compensator zeros to
offset the LC double pole, one compensator pole located to cancel the output capacitor ESR zero and one
compensator pole located between one third and one half switching frequency for high frequency noise
attenuation.
The LM2854 internal compensation components are designed to locate a pole at the origin and a pole at high
frequency as mentioned above. Furthermore, a zero is located at 8.8 kHz or 17.6 kHz for the 500 kHz or 1 MHz
options, respectively, to approximately cancel the likely location of one LC filter pole.
The three external compensation components, R
FB1
, R
COMP
and C
COMP
, are selected to position a zero at or
below the LC pole location and a pole to cancel the ESR zero. The voltage loop crossover frequency, f
loop
, is
usually selected between one tenth to one fifth of the switching frequency
0.1f
SW
≤ f
loop
≤ 0.2f
SW
(13)
A simple solution for the required external compensation capacitor, C
COMP
, with type III voltage mode control can
be expressed as
(14)
where the constant α is nominally 0.038 or 0.075 for the 500 kHz or 1 MHz options, respectively. This assumes a
compensator pole cancels the output capacitor ESR zero. Furthermore, since the modulator gain is proportional
to V
IN
, the loop crossover frequency increases with V
IN
. Thus, it is recommended to design the loop at maximum
expected V
IN
.
The upper feedback resistor, R
FB1
, is selected to provide adequate mid-band gain and to locate a zero at or
below the LC pole frequency. The series resistor, R
COMP
, is selected to locate a pole at the ESR zero frequency.
Thus
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