Datasheet

V
OUT
= 0.8V
R
FB1
+ R
FB2
R
FB2
PVIN
AVIN
EN
AGND
PGND
FB
SW
LM2854
SS
R
EN2
R
EN1
V
IN
C
IN
V
OUT1
V
OUT2
L
O
C
O
PVIN
AVIN
EN
AGND
PGND
FB
SW
LM2854
SS
R
EN2
R
EN1
V
IN
C
IN
V
IN(UVLO)
= 1.23V
R
EN1
+ R
EN2
R
EN2
VOLTAGE
TIME
SIMULTANEOUS STARTUP
V
OUT2
EN
V
OUT1
LM2854
SNVS560C –MARCH 2008–REVISED APRIL 2013 www.ti.com
ENABLE AND UVLO
Using a resistor divider from VIN to EN as shown in the schematic diagram below, the input voltage at which the
part begins switching can be increased above the normal input UVLO level according to
(10)
For example, suppose that the required input UVLO level is 3.69V. Choosing R
EN2
= 10 kΩ, then we calculate
R
EN1
= 20 kΩ.
Alternatively, the EN pin can be driven from another voltage source to cater for system sequencing requirements
commonly found in FPGA and other multi-rail applications. The following schematic shows an LM2854 that is
sequenced to start based on the voltage level of a master system rail.
OUTPUT VOLTAGE SETTING
A divider resistor network from V
OUT
to the FB pin determines the desired output voltage as follows
(11)
R
FB1
is defined based on the voltage loop requirements and R
FB2
is then selected for the desired output voltage.
These resistors are normally selected as 0.5% or 1% tolerance.
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