Datasheet

LM2854
www.ti.com SNVS560C –MARCH 2008–REVISED APRIL 2013
PRE-BIASED STARTUP CAPABILITY
The LM2854 is in a pre-biased state when the device starts up with an output voltage greater than zero. This
often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. The output can be
pre-biased in these applications through parasitic conduction paths from one supply rail to another. Even though
the LM2854 is a synchronous converter, it will not pull the output low when a pre-bias condition exists. The
LM2854 will not sink current during start up until the soft-start voltage exceeds the voltage on the FB pin. Since
the device can not sink current it protects the load from damage that might otherwise occur if current is
conducted through the parasitic paths of the load.
FEEDBACK VOLTAGE ACCURACY
The FB pin is connected to the inverting input of the voltage loop error amplifier and during closed loop operation
its reference voltage is 0.8V. The FB voltage is accurate to within -1.25% / +1.0% over temperature. Additionally,
the LM2854 contains error nulling circuitry to substantially eliminate the feedback voltage over temperature drift
as well as the long term aging effects of the internal amplifiers. In addition, the 1/f noise of the bandgap amplifier
and reference are dramatically reduced. The manifestation of this circuit action is that the duty cycle will have two
slightly different but distinct operating points, each evident every other switching cycle. The oscilloscope plot
shown previously of the SW pin with infinite persistence set shows this behavior. No discernible effect is evident
on the output due to LC filter attenuation. For further information, a Texas Instruments white paper is available on
this topic.
POSITIVE CURRENT LIMIT
The LM2854 employs lossless cycle-by-cycle high-side current limit circuitry to limit the peak current through the
high-side FET. The peak current limit threshold, denoted I
CL
, is nominally set at 6A internally. When a current
greater than I
CL
is sensed through the PFET, its on-time is immediately terminated and the NFET is activated.
The NFET stays on for the entire next four switching cycles (effectively four PFET pulses are skipped). During
these skipped pulses, the voltage on the soft-start pin is reduced by discharging the soft-start capacitor by a
current sink on the soft-start pin of nominally 6 µA or 14 µA for the 500 kHz or 1 MHz options, respectively.
Subsequent over-current events will drain more and more charge from the soft-start capacitor, effectively
decreasing the reference voltage as the output droops due to the pulse skipping. Reactivation of the soft-start
circuitry ensures that when the over-current situation is removed, the part will resume normal operation smoothly.
NEGATIVE CURRENT LIMIT
The LM2854 implements negative current limit detection circuitry to prevent large negative current in the
inductor. When the negative current sensed in the low-side NFET is below approximately -0.4A, the present
switching cycle is immediately terminated and both FETs are turned off. When both FETs are off, the negative
inductor current originally flowing in the low-side NFET and into the SW pin commutates to the high-side PFET’s
body diode and ramps back to zero. At this point, the SW pin becomes a high impedance node and ringing can
be observed on the SW node as the stored energy in the inductor is dissipated while resonating with the parasitic
nodal capacitance.
OVER-TEMPERATURE PROTECTION
When the LM2854 senses a junction temperature greater than 165°C, both switching FETs are turned off and the
part enters a sleep state. Upon sensing a junction temperature below 155°C, the part will re-initiate the soft-start
sequence and begin switching once again. This feature is provided to prevent catastrophic failure due to
excessive thermal dissipation.
LOOP COMPENSATION
The LM2854 preserves flexibility by integrating the control components around the error amplifier while utilizing
three small external compensation components from V
OUT
to FB. An integrated type II (two pole, one zero)
voltage-mode compensation network is featured. To ensure stability, an external resistor and small value
capacitor can be added across the upper feedback resistor as a pole-zero pair to complete a type III (three pole,
two zero) compensation network. For correct selection of these components, see the design section of this
datasheet.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM2854