Datasheet

'I
L
=
550 kHz x 4.7 PH
(5.5V ± 2.5V)
= 0.528A
¨
¨
©
§
2.5V
5.5V
¨
¨
©
§
'I
L
=
f
SW
x L
O
D x (V
IN
- V
OUT
)
www.ti.com PCB Layout
5.3 L
O
and C
O
The selection of the output filter components L
O
and C
O
, are intrinsically linked, as both of these
parameters affect the stability of the system, and various characteristics of the output voltage. First, a 4.7
μH inductor is chosen to allow stable operation over the entire input voltage range (as per the datasheet
recommendations) from 3.0V to 5.5V. The size of the inductor also directly affects the amplitude of the
inductor current ripple. This amplitude can be calculated from the following equation:
(5)
From this, it follows that the maximum inductor current ripple using standard operating conditions of the
LM2853 and a 4.7 μH inductor will occur at V
IN
= 5.5V, and V
OUT
= 2.5V. Under these conditions the
inductor current ripple is given as:
(6)
This means an inductor must be selected with a saturation current higher than 3.264A to ensure that the
inductor will never saturate during normal operating conditions. A Coilcraft DO3316P, 4.7 µH inductor
provides the necessary current handling capabilities (I
SAT
= 5.4A) in a relatively small footprint.
The ESR of the output capacitor affects both the ripple voltage at the output and the overall stability of the
loop. In order to keep the output voltage ripple manageable under all operating conditions, an ESR value
of 50 mΩ is selected. As per the datasheet recommendations, a capacitance of 220 μF will ensure stability
regardless of V
IN
and V
OUT
when coupled with 4.7 μH inductor and 50 mΩ ESR. An AVX low-ESR 6.3V
tantalum capacitor provides the necessary ESR and capacitance to stabilize the loop and control the
output voltage ripple, with suitable voltage derating for up to a 3.3V output.
6 PCB Layout
The PCB layout of the LM2853 demo board was designed to occupy as little board space as possible,
while still following sound layout guidelines and techniques. The input capacitor, C
IN
is placed as close as
possible to the PVIN pins and the PGND pins, to minimize stray resistance and inductance between C
IN
and the LM2853. Likewise, the AVIN bypass capacitor is placed as close as possible to the AVIN and
SGND pins. PGND and SGND are connected to each other and the ground plane at a single point, the
exposed pad of the LM2853. Also, in order to help conduct heat to the ground plane and away from the
LM2853, an array of vias is used to connect the exposed pad to the ground plane, instead of a single via.
Finally, the sense pin trace is intentionally routed away from the SW node to minimize any EMI pickup.
3
SNVA180A–October 2006–Revised April 2013 AN-1513 LM2853 Evaluation Board
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated