Datasheet

EN
SGND
SS
NC
PVIN
PVIN
SNS
NC
NC
PGND
PGND
SW
SW
AVIN
LM2852
1
2
3
4
5
7
6
14
13
12
11
10
8
9
I
LOAD
(A)
0.1 1.0 10
84
86
88
90
92
94
96
EFFICIENCY (%)
PVIN = 3.3V
LM2852
SNVS325D –JANUARY 2005–REVISED APRIL 2013 www.ti.com
Figure 1. Efficiency vs I
LOAD
Connection Diagram
Figure 2. 14-Pin HTSSOP – Top View
See Package Number PWP0014A
PIN DESCRIPTIONS
AVIN (Pin 1): Chip bias input pin. This provides power to the logic of the chip. Connect to the input voltage or a separate rail.
EN (Pin 2): Enable. Connect this pin to ground to disable the chip; connect to AVIN or leave floating to enable the chip; enable is internally
pulled up.
SGND (Pin 3): Signal ground.
SS (Pin 4): Soft-start pin. Connect this pin to a small capacitor to control startup. The soft-start capacitance range is restricted to values 1
nF to 50 nF.
NC (Pins 5, 12 and 13): No connect. These pins must be tied to ground or left floating in the application.
PVIN (Pins 6, 7): Input supply pin. PVIN is connected to the input voltage. This rail connects to the source of the internal power PFET.
SW (Pins 8, 9): Switch pin. Connect to the output inductor.
PGND (Pins 10, 11): Power ground. Connect this to an internal ground plane or other large ground plane.
SNS (Pin 14): Output voltage sense pin. Connect this pin to the output voltage as close to the load as possible.
Exposed Pad: Connect to ground.
2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM2852