Datasheet
LM2833
SNVS505E –MAY 2008–REVISED APRIL 2013
www.ti.com
I
Q
is the quiescent operating current, and is typically around 3.2mA for the LM2833X, and 4.3mA for the
LM2833Z.
An example of efficiency calculation for a typical application is shown in Table 1:
Table 1. Power Loss Tabulation
Conditions Power loss
V
IN
5V
V
OUT
3.3V
I
OUT
3.0A P
OUT
9.9W
V
D
0.33V P
DIODE
277mW
R
DS(ON)
56mΩ P
COND
363mW
f
SW
1.5MHz
T
RISE
10ns
P
SW
225mW
T
FALL
10ns
IND
DCR
28mΩ P
IND
252mW
I
Q
3.2mA P
Q
16mW
η 89.7%
D is calculated to be 0.72
P
LOSS
= Σ ( P
COND
+ P
SW
+ P
Q
+ P
IND
+ P
DIODE
) (30)
P
LOSS
= 1.133W (31)
PCB LAYOUT CONSIDERATIONS
When planning layout there are a few things to consider to achieve a clean, regulated output. The most important
consideration is the close coupling of the GND connections of the input capacitor C1 and the catch diode D1.
These ground ends should be close to one another and be connected to the GND plane with at least two
through-holes. Place these components as close to the IC as possible. The next consideration is the location of
the GND connection of the output capacitor C2, which should be near the GND connections of C1 and D1. There
should be a continuous ground plane on the bottom layer of a two-layer board except under the switching node
island. The signal ground SGND (pin 3) and power ground PGND (pin 6) should be tied together and connected
to ground plane through vias.
The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise pickup
that causes inaccurate regulation. The feedback resistors should be placed as close as possible to the IC, with
the GND of R2 placed as close as possible to the SGND of the IC. The V
OUT
trace to R1 should be routed away
from the inductor and any other traces that are switching.
High AC currents flow through the V
IN
, SW and V
OUT
traces, so they should be as short and wide as possible.
Radiated noise can be decreased by choosing a shielded inductor.
The remaining components should also be placed as close as possible to the IC. Please see Application Note
AN-1229 SNVA054 for further considerations and the LM2833 demo board as an example of a four-layer layout.
18 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM2833