Datasheet

C
CLK
External Clock
Signal
To FREQ/SYNC Pin
R
FADJ
R
FB1
V
OUT
=
R
FB1
R
FB2
+
V
FB
(V
FB
= 0.6V)
C
SS
=
t
SS
60
LM2745, LM2748
www.ti.com SNOSAL2E –APRIL 2005–REVISED APRIL 2013
APPLICATION INFORMATION
The LM2745/8 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is
designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high
efficiency buck converters. It has output shutdown (SD), input undervoltage lock-out (UVLO) mode and power
good (PWGD) flag (based on overvoltage and undervoltage detection). The overvoltage and undervoltage
signals are OR-gated to drive the power good signal and provide a logic signal to the system if the output voltage
goes out of regulation. Current limit is achieved by sensing the voltage V
DS
across the low side MOSFET. The
LM2745/8 is also able to start-up with the output pre-biased with a load. The LM2745 also allows for the
switching frequency to be synchronized with an external clock source.
START UP/SOFT-START
When V
CC
exceeds 2.79V and the shutdown pin (SD) sees a logic high, the soft-start period begins. Then an
internal, fixed 10 µA source begins charging the soft-start capacitor. During soft-start the voltage on the soft-start
capacitor C
SS
is connected internally to the non-inverting input of the error amplifier. The soft-start period lasts
until the voltage on the soft-start capacitor exceeds the LM2745/8 reference voltage of 0.6V. At this point the
reference voltage takes over at the non-inverting error amplifier input. The capacitance of C
SS
determines the
length of the soft-start period, and can be approximated by:
Where C
SS
is in µF and t
SS
is in ms.
During soft start the Power Good flag is forced low and it is released when the FB pin voltage reaches 70% of
0.6V. At this point the chip enters normal operation mode, and the output overvoltage and undervoltage
monitoring starts.
SETTING THE OUTPUT VOLTAGE
The LM2745/8 regulates the output voltage by controlling the duty cycle of the high side and low side MOSFETs
(see Typical Application Circuit).The equation governing output voltage is:
SETTING THE SWITCHING FREQUENCY
During fixed-frequency mode of operation the PWM frequency is adjustable between 50 kHz and 1 MHz and is
set by an external resistor, R
FADJ
, between the FREQ/SYNC pin and ground. The resistance needed for a
desired frequency is approximated by the curve FREQUENCY vs. FREQUENCY ADJUST RESISTOR in the
Typical Performance Characteristics section.
When it is desired to synchronize the switching frequency with an external clock source, the LM2745 has the
unique ability to synchronize from this external source within the range of 250 kHz to 1 MHz. The external clock
signal should be AC coupled to the FREQ/SYNC pin as shown below in Figure 17, where the R
FADJ
is chosen so
that the fixed frequency is approximately within ±30% of the external synchronizing clock frequency. An internal
protection diode clamps the low level of the synchronizing signal to approximately -0.5V. The internal clock
sychronizes to the rising edge of the external clock.
Figure 17. AC Coupled Clock
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