Datasheet

8 PA
17 PA
Bias Enable
Soft-Start Enable
1.25V
10k
SD
+
-
t = 5 ms
V
OUT1
V
OUT2
5V
1.8V
V
SD-IH
1.08V
LM2745, LM2748
www.ti.com SNOSAL2E –APRIL 2005–REVISED APRIL 2013
For example, if the master supply output voltage slew rate was 1V/ms and the desired delay time between the
startup of the master supply and LM2745/8 output voltage was 5 ms, then the desired SD pin slew rate would be
(1.08V/5 ms) = 0.216V/ms. Due to the internal impedance of the SD pin, the maximum recommended value for
R
S2
is 1 kΩ. To achieve the desired slew rate, R
S1
would then be 274Ω. A timing diagram for this example is
shown in Figure 23.
Figure 23. Delay for Sequencing
SD PIN IMPEDANCE
When connecting a resistor divider to the SD pin of the LM2745/8 some care has to be taken. Once the SD
voltage goes above V
SD-IH
, a 17 µA pull-up current is activated as shown in Figure 24. This current is used to
create the internal hysteresis (≊170 mV); however, high external impedances will affect the SD pin logic
thresholds as well. The external impedance used for the sequencing divider network should preferably be a small
fraction of the impedance of the SD pin for good performance (around 1 kΩ).
Figure 24. SD Pin Logic
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM2745 LM2748