Datasheet

R
FADJ
= -5.93 + 3.06
10
7
f
SW
+ 0.24
10
12
(f
SW
)
2
R
FB1
V
OUT
=
R
FB1
R
FB2
+
V
FB
(V
FB
= 0.6V)
C
SS
=
t
SS
60
LM2743
SNVS276G –APRIL 2004–REVISED MARCH 2013 www.ti.com
APPLICATION INFORMATION
THEORY OF OPERATION
The LM2743 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is
designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high
efficiency buck converters. It has output shutdown (SD), input under-voltage lock-out (UVLO) mode and power
good (PWGD) flag (based on over-voltage and under-voltage detection). The over-voltage and under-voltage
signals are logically OR'ed to drive the power good signal and provide a logic signal to the system if the output
voltage goes out of regulation. Current limit is achieved by sensing the voltage V
DS
across the low side MOSFET.
START UP/SOFT-START
When V
CC
exceeds 2.76V and the shutdown pin (SD) sees a logic high, the soft-start period begins. Then an
internal, fixed 10 µA source begins charging the soft-start capacitor. During soft-start the voltage on the soft-start
capacitor C
SS
is connected internally to the non-inverting input of the error amplifier. The soft-start period lasts
until the voltage on the soft-start capacitor exceeds the LM2743 reference voltage of 0.6V. At this point the
reference voltage takes over at the non-inverting error amplifier input. The capacitance of C
SS
determines the
length of the soft-start period, and can be approximated by:
Where C
SS
is in µF and t
SS
is in ms.
During soft start the Power Good flag is forced low and it is released when the FB pin voltage reaches 70% of
0.6V. At this point the chip enters normal operation mode, and the output overvoltage and undervoltage
monitoring starts.
NORMAL OPERATION
While in normal operation mode, the LM2743 regulates the output voltage by controlling the duty cycle of the
high side and low side MOSFETs (see Figure 1). The equation governing output voltage is:
The PWM frequency is adjustable between 50 kHz and 1 MHz and is set by an external resistor, R
FADJ
, between
the FREQ pin and ground. The resistance needed for a desired frequency is approximately:
Where f
SW
is in Hz and R
FADJ
is in kΩ.
TRACKING A VOLTAGE LEVEL
The LM2743 can track the output of a master power supply during soft-start by connecting a resistor divider to
the SS/TRACK pin. In this way, the output voltage slew rate of the LM2743 will be controlled by the master
supply for loads that require precise sequencing. When the tracking function is used no soft-start capacitor
should be connected to the SS/TRACK pin. Otherwise, a C
SS
value of at least 1 nF between the soft-start pin
and ground should be used.
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