Datasheet

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LM2742
www.ti.com SNVS266C –MARCH 2004–REVISED MARCH 2013
Control Loop Components
The circuit is this design example and the others shown in the Example Circuits section have been compensated
to improve their DC gain and bandwidth. The result of this compensation is better line and load transient
responses. For the LM2742, the top feedback divider resistor, Rfb2, is also a part of the compensation. For the
10A, 5V to 1.2V design, the values are:
Cc1 = 4.7pF 10%, Cc2 = 1nF 10%, Rc = 229kΩ 1%. These values give a phase margin of 63° and a bandwidth
of 29.3kHz.
Support Capacitors and Resistors
The Cinx capacitors are high frequency bypass devices, designed to filter harmonics of the switching frequency
and input noise. Two 1µF ceramic capacitors with a sufficient voltage rating (10V for the Circuit of Figure 32) will
work well in almost any case.
R
IN
and C
IN
are standard filter components designed to ensure smooth DC voltage for the chip supply.
Depending on noise, R
IN
should be 10 to 100Ω, and C
IN
should be between 0.1 and 2.2 µF. C
BOOT
is the
bootstrap capacitor, and should be 0.1µF. (In the case of a separate, higher supply to the BOOT pin, this 0.1µF
cap can be used to bypass the supply.) Using a Schottky device for the bootstrap diode allows the minimum drop
for both high and low side drivers. The On Semiconductor BAT54 or MBR0520 work well.
Rp is a standard pull-up resistor for the open-drain power good signal, and should be 10kΩ. If this feature is not
necessary, it can be omitted.
R
CS
is the resistor used to set the current limit. Since the design calls for a peak current magnitude (Io + 0.5 *
ΔI
o
) of 12A, a safe setting would be 15A. (This is well below the saturation current of the output inductor, which is
25A.) Following the equation from the Current Limit section, use a 3.3kΩ resistor.
R
FADJ
is used to set the switching frequency of the chip. Following the equation in the Theory of Operation
section, the closest 1% tolerance resistor to obtain f
SW
= 300kHz is 88.7kΩ.
C
SS
depends on the users requirements. Based on the equation for C
SS
in the Theory of Operation section, for a
3ms delay, a 12nF capacitor will suffice.
EFFICIENCY CALCULATIONS
A reasonable estimation of the efficiency of a switching controller can be obtained by adding together the loss is
each current carrying element and using the equation:
(14)
The following shows an efficiency calculation to complement the Circuit of Figure 32. Output power for this circuit
is 1.2V x 10A = 12W.
Chip Operating Loss
P
IQ
= I
Q-V
CC
*V
CC
(15)
2mA x 5V = 0.01W
FET Gate Charging Loss
P
GC
= n * V
CC
* Q
GS
* f
OSC
(16)
The value n is the total number of FETs used. The Si4442DY has a typical total gate charge, Q
GS
, of 36nC and
an r
ds-on
of 4.1mΩ. For a single FET on top and bottom: 2*5*36E
-9
*300,000 = 0.108W
FET Switching Loss
P
SW
= 0.5 * V
in
* I
O
* (t
r
+ t
f
)* f
OSC
(17)
The Si4442DY has a typical rise time t
r
and fall time t
f
of 11 and 47ns, respectively. 0.5*5*10*58E
-9
*300,000 =
0.435W
FET Conduction Loss
P
Cn
= 0.533W (18)
Input Capacitor Loss
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