Datasheet

o
MAX
o
V
ESR
I
'
'
LM2742
SNVS266C –MARCH 2004–REVISED MARCH 2013 www.ti.com
Output Inductor
The output inductor forms the first half of the power stage in a Buck converter. It is responsible for smoothing the
square wave created by the switching action and for controlling the output current ripple. (ΔI
o
) The inductance is
chosen by selecting between tradeoffs in output ripple, efficiency, and response time. The smaller the output
inductor, the more quickly the converter can respond to transients in the load current. If the inductor value is
increased, the ripple through the output capacitor is reduced and thus the output ripple is reduced. As shown in
the efficiency calculations, a smaller inductor requires a higher switching frequency to maintain the same level of
output current ripple. An increase in frequency can mean increasing loss in the FETs due to the charging and
discharging of the gates. Generally the switching frequency is chosen so that conduction loss outweighs
switching loss. The equation for output inductor selection is:
(11)
A good range for ΔI
o
is 25 to 50% of the output current. In the past, 30% was considered a maximum value for
output currents higher than about 2Amps, but as output capacitor technology improves the ripple current can be
allowed to increase. Plugging in the values for output current ripple, input voltage, output voltage, switching
frequency, and assuming a 40% peak-to-peak output current ripple yields an inductance of 1.5µH. The output
inductor must be rated to handle the peak current (also equal to the peak switch current), which is (Io + 0.5*ΔI
o
).
This is 12A for a 10A design. The Coilcraft D05022-152HC is 1.5µH, is rated to 15Arms, and has a DCR of 4mΩ.
Output Capacitor
The output capacitor forms the second half of the power stage of a Buck switching converter. It is used to control
the output voltage ripple (ΔV
o
) and to supply load current during fast load transients.
In this example the output current is 10A and the expected type of capacitor is an aluminum electrolytic, as with
the input capacitors. (Other possibilities include ceramic, tantalum, and solid electrolyte capacitors, however the
ceramic type often do not have the large capacitance needed to supply current for load transients, and tantalums
tend to be more expensive than aluminum electrolytic.) Aluminum capacitors tend to have very high capacitance
and fairly low ESR, meaning that the ESR zero, which affects system stability, will be much lower than the
switching frequency. The large capacitance means that at switching frequency, the ESR is dominant, hence the
type and number of output capacitors is selected on the basis of ESR. One simple formula to find the maximum
ESR based on the desired output voltage ripple, ΔV
o
and the designed output current ripple, ΔI
o
, is:
(12)
In this example, in order to maintain a 2% peak-to-peak output voltage ripple and a 40% peak-to-peak inductor
current ripple, the required maximum ESR is 6mΩ. Three Sanyo 10MV5600AX capacitors in parallel will give an
equivalent ESR of 6mΩ. The total bulk capacitance of 16.8mF is enough to supply even severe load transients.
Using the same capacitors for both input and output also keeps the bill of materials simple.
MOSFETS
MOSFETS are a critical part of any switching controller and have a direct impact on the system efficiency. In this
case the target efficiency is 85% and this is the variable that will determine which devices are acceptable. Loss
from the capacitors, inductors, and the LM2742 is detailed in the Efficiency section, and come to about 0.54W.
To meet the target efficiency, this leaves 1.45W for the FET conduction loss, gate charging loss, and switching
loss. Switching loss is particularly difficult to estimate because it depends on many factors. When the load
current is more than about 1 or 2 amps, conduction losses outweigh the switching and gate charging losses. This
allows FET selection based on the R
DSON
of the FET. Adding the FET switching and gate-charging losses to the
equation leaves 1.2W for conduction losses. The equation for conduction loss is:
P
Cnd
= D(I
2
o
* R
DSON
*k) + (1-D)(I
2
o
* R
DSON
*k) (13)
The factor k is a constant which is added to account for the increasing R
DSON
of a FET due to heating. Here, k =
1.3. The Si4442DY has a typical R
DSON
of 4.1mΩ. When plugged into the equation for P
CND
the result is a loss of
0.533W. If this design were for a 5V to 2.5V circuit, an equal number of FETs on the high and low sides would be
the best solution. With the duty cycle D = 0.24, it becomes apparent that the low side FET carries the load
current 76% of the time. Adding a second FET in parallel to the bottom FET could improve the efficiency by
lowering the effective R
DSON
. The lower the duty cycle, the more effective a second or even third FET can be. For
a minimal increase in gate charging loss (0.054W) the decrease in conduction loss is 0.15W. What was an 85%
design improves to 86% for the added cost of one SO-8 MOSFET.
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