Datasheet

 
IN O
PK-CL LIM OSC
V V
I I T 200 ns
L

 
I
LIM
I
L
D
Normal Operation Current Limit
LM2742
SNVS266C –MARCH 2004–REVISED MARCH 2013 www.ti.com
beginning of a clock cycle. In current limit mode, by contrast, the high side FET on pulse is skipped. This causes
inductor current to fall. Unlike a normal operation switching cycle, however, in a current limit mode switching
cycle the high side FET will turn on as soon as inductor current has fallen to the current limit threshold. The
LM2727/37 will continue to skip high side FET pulses until the inductor current peak is below the current limit
threshold, at which point the system resumes normal operation.
Figure 30. Current Limit Threshold
Unlike a high side FET current sensing scheme, which limits the peaks of inductor current, low side current
sensing is only allowed to limit the current during the converter off-time, when inductor current is falling.
Therefore in a typical current limit plot the valleys are normally well defined, but the peaks are variable, according
to the duty cycle. The PWM error amplifier and comparator control the off pulse of the high side FET, even
during current limit mode, meaning that peak inductor current can exceed the current limit threshold. Assuming
that the output inductor does not saturate, the maximum peak inductor current during current limit mode can be
calculated with the following equation:
(6)
Where T
OSC
is the inverse of switching frequency f
OSC
. The 200ns term represents the minimum off-time of the
duty cycle, which ensures enough time for correct operation of the current sensing circuitry. See the plots entitled
Peak Current During Current Limit in the Typical Performance Characteristics section.
In order to minimize the time period in which peak inductor current exceeds the current limit threshold, the IC
also discharges the soft start capacitor through a fixed 95 µA source. The output of the LM2727/37 internal error
amplifier is limited by the voltage on the soft start capacitor. Hence, discharging the soft start capacitor reduces
the maximum duty cycle D of the controller. During severe current limit this reduction in duty cycle will reduce the
output voltage if the current limit conditions last for an extended time. Output inductor current will be reduced in
turn to a flat level equal to the current limit threshold. The third benefit of the soft start capacitor discharge is a
smooth, controlled ramp of output voltage when the current limit condition is cleared. During the first few
nanoseconds after the low side gate turns on, the low side FET body diode conducts. This causes an additional
0.7V drop in V
DS
. The range of V
DS
is normally much lower. For example, if R
DSON
were 10mΩ and the current
through the FET was 10A, V
DS
would be 0.1V. The current limit would see 0.7V as a 70A current and enter
current limit immediately. Hence current limit is masked during the time it takes for the high side switch to turn off
and the low side switch to turn on.
SHUT DOWN
If the shutdown pin SD is pulled low, the LM2742 discharges the soft start capacitor through a MOSFET switch.
The high side and low side switches are turned off. The LM2742 remains in this state until SD is released.
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