Datasheet

R
T
JA
=
165
o
C - 132
o
C
0.881 W
= 37.46
o
C/W
LM27341, LM27342, LM27341-Q1, LM27342-Q1
SNVS497E –NOVEMBER 2008–REVISED APRIL 2013 www.ti.com
METHOD 3 EXAMPLE
The operating conditions are the same as the previous Efficiency Calculation:
V
IN
= 12V V
OUT
= 3.3V I
OUT
= 2A
f
SW
= 2 MHz V
D1
= 0.5V R
DCR
= 20 mΩ
Internal Power Losses are:
P
COND
= I
OUT
2
x R
DSON
x D
= 2
2
x 0.267Ω x .314
= 335 mW (64)
P
SW
= (V
IN
x I
OUT
x f
SW
x t
FALL
)
= (12V x 2A x 2 MHz x 10nS)
= 480 mW (65)
P
Q
= I
Q
x V
IN
= 1.5 mA x 12V
= 29 mW (66)
P
BOOST
= I
BOOST
x V
BOOST
= 7 mA x 4.5V
= 37 mW (67)
P
INTERNAL
= P
COND
+ P
SW
+ P
Q
+ P
BOOST
= 881 mW (68)
Using a Texas Instruments MSOP-PowerPad evaluation board to determine the R
θJA
of the board. The four layer
PCB is constructed using FR4 with 2oz copper traces. There is a ground plane on the internal layer directly
beneath the device, and a ground plane on the bottom layer. The ground plane is accessed by fourteen 10 mil
vias. The board measures 2in x 2in (50.8mm x 50.8mm). It was placed in an oven with no forced airflow.
The ambient temperature was raised to 132 °C, and at that temperature, the device went into thermal shutdown.
R
θJA
can now be calculated.
(69)
To keep the Junction temperature below 125 °C for this layout, the ambient temperature must stay below 92 °C.
T
A_MAX
= T
J_MAX
- (R
θJA
x P
INTERNAL
) (70)
T
A_MAX
= 125 °C - (37.46 °C/W x 0.881 W) (71)
T
A_MAX
= 92 °C (72)
This calculation of the maximum ambient temperature is only 2.3 °C different from the calculation using method
2. The methods described above to find the junction temperature in the MSOP-PowerPad package can also be
used to calculate the junction temperature in the SON package. The 10-pin SON package has a R
θJC
= 9.1°C/W,
while R
θJA
can vary depending on the layout. R
θJA
can be calculated in the same manner as described in method
3.
PCB Layout Considerations
COMPACT LAYOUT
The performance of any switching converter depends as much upon the layout of the PCB as the component
selection. The following guidelines will help the user design a circuit with maximum rejection of outside EMI and
minimum generation of unwanted EMI.
Parasitic inductance can be reduced by keeping the power path components close together and keeping the
area of the loops small, on which high currents travel. Short, thick traces or copper pours (shapes) are best. In
particular, the switch node (where L1, D1, and the SW pin connect) should be just large enough to connect all
three components without excessive heating from the current it carries. The LM27341/LM27342 operates in two
distinct cycles (see Figure 32) whose high current paths are shown below in Figure 39:
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