Datasheet

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LM27341, LM27342, LM27341-Q1, LM27342-Q1
www.ti.com SNVS497E –NOVEMBER 2008–REVISED APRIL 2013
Figure 39. Buck Converter Current Loops
The dark grey, inner loop represents the high current path during the MOSFET on-time. The light grey, outer loop
represents the high current path during the off-time.
GROUND PLANE AND SHAPE ROUTING
The diagram of Figure 39 is also useful for analyzing the flow of continuous current vs. the flow of pulsating
currents. The circuit paths with current flow during both the on-time and off-time are considered to be continuous
current, while those that carry current during the on-time or off-time only are pulsating currents. Preference in
routing should be given to the pulsating current paths, as these are the portions of the circuit most likely to emit
EMI. The ground plane of a PCB is a conductor and return path, and it is susceptible to noise injection just like
any other circuit path. The path between the input source and the input capacitor and the path between the catch
diode and the load are examples of continuous current paths. In contrast, the path between the catch diode and
the input capacitor carries a large pulsating current. This path should be routed with a short, thick shape,
preferably on the component side of the PCB. Multiple vias in parallel should be used right at the pad of the input
capacitor to connect the component side shapes to the ground plane. A second pulsating current loop that is
often ignored is the gate drive loop formed by the SW and BOOST pins and boost capacitor C
BOOST
. To minimize
this loop and the EMI it generates, keep C
BOOST
close to the SW and BOOST pins.
FB LOOP
The FB pin is a high-impedance input, and the loop created by R2, the FB pin and ground should be made as
small as possible to maximize noise rejection. R2 should therefore be placed as close as possible to the FB and
GND pins of the IC.
PCB SUMMARY
1. Minimize the parasitic inductance by keeping the power path components close together and keeping the
area of the high-current loops small.
2. The most important consideration when completing the layout is the close coupling of the GND connections
of the C
IN
capacitor and the catch diode D1. These ground connections should be immediately adjacent, with
multiple vias in parallel at the pad of the input capacitor connected to GND. Place C
IN
and D1 as close to the
IC as possible.
3. Next in importance is the location of the GND connection of the C
OUT
capacitor, which should be near the
GND connections of C
IN
and D1.
4. There should be a continuous ground plane on the copper layer directly beneath the converter. This will
reduce parasitic inductance and EMI.
5. The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise
pickup and inaccurate regulation. The feedback resistors should be placed as close as possible to the IC,
with the GND of R2 placed as close as possible to the GND of the IC. The V
OUT
trace to R1 should be routed
away from the inductor and any other traces that are switching.
6. High AC currents flow through the V
IN
, SW and V
OUT
traces, so they should be as short and wide as
possible. However, making the traces wide increases radiated noise, so the layout designer must make this
trade-off. Radiated noise can be decreased by choosing a shielded inductor.
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