Datasheet

2
3
4
7
9
8
PVIN
SW
EN
DAP
AVIN
GND
BOOST
6
10
1
5
SYNC
FB
SW
PVIN
1
2
3
4
SW
BOOST
GND
AVIN
PVIN
PVIN
5
FB
EN
SYNC
SW
6
7
8
9
10
DAP
LM27341/2
V
IN
PVIN
EN
BOOST
SW
FB
GND / DAP
V
OUT
C2
L1
C1
C3
R1
R2
D1
SYNC
AVIN
CLK
ON
OFF
LM27341, LM27342, LM27341-Q1, LM27342-Q1
SNVS497E –NOVEMBER 2008–REVISED APRIL 2013 www.ti.com
Typical Application Circuit
Figure 1. Figure 2. Efficiency vs Load Current
V
OUT
= 5V, f
sw
= 2 MHz
Connection Diagram
Figure 3. 10-Lead SON (Top View) Figure 4. 10-Lead MSOP-PowerPad (Top View)
See DSC0010A Package See DGQ0010A Package
PIN DESCRIPTIONS
Pin Name Function
1, 2 SW Output switch. Connects to the inductor, catch diode, and bootstrap capacitor.
3 BOOST Boost voltage that drives the internal NMOS control switch. A bootstrap capacitor is connected between the
BOOST and SW pins.
4 EN Enable control input. Logic high enables operation. Do not allow this pin to float or be greater than V
IN
+ 0.3V.
5 SYNC Frequency synchronization input. Drive this pin with an external clock or pulse train. Ground it to use the
internal clock.
6 FB Feedback pin. Connect FB to the external resistor divider to set output voltage.
7 GND Signal and Power Ground pin. Place the bottom resistor of the feedback network as close as possible to this
pin for accurate regulation.
8 AVIN Supply voltage for the control circuitry.
9, 10 PVIN Supply voltage for output power stage. Connect a bypass capacitor to this pin.
DAP GND Signal / Power Ground and thermal connection. Tie this directly to GND (pin 7). See Application Information
regarding optimum thermal layout.
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Product Folder Links: LM27341 LM27342 LM27341-Q1 LM27342-Q1