Datasheet

LM2733

SNVS209E –NOVEMBER 2002–REVISED APRIL 2013

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Block Diagram

THEORY OF OPERATION

The LM2733 is a switching converter IC that operates at a fixed frequency (0.6 or 1.6 MHz) using current-mode

control for fast transient response over a wide input voltage range and incorporate pulse-by-pulse current limiting

protection. Because this is current mode control, a 50 mΩ sense resistor in series with the switch FET is used to

provide a voltage (which is proportional to the FET current) to both the input of the pulse width modulation

(PWM) comparator and the current limit amplifier.

At the beginning of each cycle, the S-R latch turns on the FET. As the current through the FET increases, a

voltage (proportional to this current) is summed with the ramp coming from the ramp generator and then fed into

the input of the PWM comparator. When this voltage exceeds the voltage on the other input (coming from the

Gm amplifier), the latch resets and turns the FET off. Since the signal coming from the Gm amplifier is derived

from the feedback (which samples the voltage at the output), the action of the PWM comparator constantly sets

the correct peak current through the FET to keep the output volatge in regulation.

Q1 and Q2 along with R3 - R6 form a bandgap voltage reference used by the IC to hold the output in regulation.

The currents flowing through Q1 and Q2 will be equal, and the feedback loop will adjust the regulated output to

maintain this. Because of this, the regulated output is always maintained at a voltage level equal to the voltage at

the FB node "multiplied up" by the ratio of the output resistive divider.

The current limit comparator feeds directly into the flip-flop, that drives the switch FET. If the FET current reaches

the limit threshold, the FET is turned off and the cycle terminated until the next clock pulse. The current limit

input terminates the pulse regardless of the status of the output of the PWM comparator.

Product Folder Links: LM2733