Datasheet

LM27x7
BOOTV
HG
LG
+
+
5V
Vo
Cb
LM2727, LM2737
www.ti.com SNVS205D –AUGUST 2002–REVISED MARCH 2013
Figure 24. BOOTV Supplied by Charge Pump
In a system without a separate, higher voltage, a charge pump (bootstrap) can be built using a diode and small
capacitor, Figure 24. The capacitor serves to maintain enough voltage between the top FET gate and source to
control the device even when the top FET is on and its source has risen up to the input voltage level.
The LM2727/37 gate drives use a BiCMOS design. Unlike some other bipolar control ICs, the gate drivers have
rail-to-rail swing, ensuring no spurious turn-on due to capacitive coupling.
POWER GOOD SIGNAL
The power good signal is the or-gated flag representing over-voltage and under-voltage protection. If the output
voltage is 18% over it's nominal value, V
FB
= 0.7V, or falls 30% below that value, V
FB
= 0.41V, the power good
flag goes low. The converter then turns off the high side gate, and turns on the low side gate. Unlike the output
(LM2727 only) the power good flag is not latched off. It will return to a logic high whenever the feedback pin
voltage is between 70% and 118% of 0.6V.
UVLO
The 4.2V turn-on threshold on V
CC
has a built in hysteresis of 0.6V. Therefore, if V
CC
drops below 3.6V, the chip
enters UVLO mode. UVLO consists of turning off the top FET, turning on the bottom FET, and remaining in that
condition until V
CC
rises above 4.2V. As with shutdown, the soft start capacitor is discharged through a FET,
ensuring that the next start-up will be smooth.
CURRENT LIMIT
Current limit is realized by sensing the voltage across the low side FET while it is on. The R
DSON
of the FET is a
known value, hence the current through the FET can be determined as:
V
DS
= I * R
DSON
(4)
The current limit is determined by an external resistor, R
CS
, connected between the switch node and the ISEN
pin. A constant current of 50µA is forced through Rcs, causing a fixed voltage drop. This fixed voltage is
compared against V
DS
and if the latter is higher, the current limit of the chip has been reached. R
CS
can be found
by using the following:
R
CS
= R
DSON
(LOW) * I
LIM
/50µA (5)
For example, a conservative 15A current limit in a 10A design with a minimum R
DSON
of 10mΩ would require a
3.3kΩ resistor. Because current sensing is done across the low side FET, no minimum high side on-time is
necessary. In the current limit mode the LM2727/37 will turn the high side off and the keep low side on for as
long as necessary. The chip also discharges the soft start capacitor through a fixed 95µA source. In this way,
smooth ramping up of the output voltage as with a normal soft start is ensured. The output of the LM2727/37
internal error amplifier is limited by the voltage on the soft start capacitor. Hence, discharging the soft start
capacitor reduces the maximum duty cycle D of the controller. During severe current limit, this reduction in duty
cycle will reduce the output voltage, if the current limit conditions lasts for an extended time.
During the first few nanoseconds after the low side gate turns on, the low side FET body diode conducts. This
causes an additional 0.7V drop in V
DS
. The range of V
DS
is normally much lower. For example, if R
DSON
were
10mΩ and the current through the FET was 10A, V
DS
would be 0.1V. The current limit would see 0.7V as a 70A
current and enter current limit immediately. Hence current limit is masked during the time it takes for the high
side switch to turn off and the low side switch to turn on.
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Product Folder Links: LM2727 LM2737