Datasheet

LM2727, LM2737
SNVS205D –AUGUST 2002–REVISED MARCH 2013 www.ti.com
APPLICATION INFORMATION
THEORY OF OPERATION
The LM2727 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is
designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high
efficiency buck converters. It has power good (PWRGD), output shutdown (SD), over voltage protection (OVP)
and under voltage protection (UVP). The over-voltage and under-voltage signals are OR gated to drive the
Power Good signal and a shutdown latch, which turns off the high side gate and turns on the low side gate if
pulled low. Current limit is achieved by sensing the voltage V
DS
across the low side FET. During current limit the
high side gate is turned off and the low side gate turned on. The soft start capacitor is discharged by a 95µA
source (reducing the maximum duty cycle) until the current is under control. The LM2737 does not latch off
during UVP or OVP, and uses the HIGH and LOW comparators for the powergood function only.
START UP
When V
CC
exceeds 4.2V and the enable pin EN sees a logic high the soft start capacitor begins charging through
an internal fixed 10µA source. During this time the output of the error amplifier is allowed to rise with the voltage
of the soft start capacitor. This capacitor, Css, determines soft start time, and can be determined approximately
by:
(1)
An application for a microprocessor might need a delay of 3ms, in which case C
SS
would be 12nF. For a different
device, a 100ms delay might be more appropriate, in which case C
SS
would be 400nF. (390 10%) During soft
start the PWRGD flag is forced low and is released when the voltage reaches a set value. At this point this chip
enters normal operation mode, the Power Good flag is released, and the OVP and UVP functions begin to
monitor Vo.
NORMAL OPERATION
While in normal operation mode, the LM2727/37 regulates the output voltage by controlling the duty cycle of the
high side and low side FETs. The equation governing output voltage is:
(2)
The PWM frequency is adjustable between 50kHz and 2MHz and is set by an external resistor, R
FADJ
, between
the FREQ pin and ground. The resistance needed for a desired frequency is approximately:
(3)
MOSFET GATE DRIVERS
The LM2727/37 has two gate drivers designed for driving N-channel MOSFETs in a synchronous mode. Power
for the drivers is supplied through the BOOTV pin. For the high side gate (HG) to fully turn on the top FET, the
BOOTV voltage must be at least one V
GS(th)
greater than Vin. (BOOTV ≥ 2*Vin) This voltage can be supplied by
a separate, higher voltage source, or supplied from a local charge pump structure. In a system such as a
desktop computer, both 5V and 12V are usually available. Hence if Vin was 5V, the 12V supply could be used for
BOOTV. 12V is more than 2*Vin, so the HG would operate correctly. For a BOOTV of 12V, the initial gate
charging current is 2A, and the initial gate discharging current is typically 6A.
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