Datasheet

LM2725, LM2726

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SNVS144D –NOVEMBER 2000–REVISED MARCH 2013

Functional Description

The LM2725/2726 drivers were designed to be used in systems supporting low-power states, such as notebook

computers’ Suspend-To-RAM (STR), etc. A typical application scenario would be powering up and powering

down the driver while having EN asserted, i.e. at logic high level. During a low-power state of the whole system

when the load is not powered, the EN input can be pulled to logic low level to shutdown the driver thus reducing

its power.

The EN pin functions as a "Chip Enable." When it is asserted high, the chip is fully powered on and fully

functional. When the EN pin is low, the power is disconnected from the internal POR (Power-On-Reset) and the

bandgap reference blocks by a P-FET. This is done to lower the quiescent current Iq from 180µA typical in

normal operation to 0.5µA typical in shutdown mode. The HG and LG drivers are still powered to maintain the

external NFETs.

The POR circuit also performs the UVLO (Under Voltage Lockout) function and, therefore, the POR must be

powered on during the driver powering up and down. This means that the EN pin must be allowed to transition

high or low with the VCC rail. Having the EN pin low during startup prevents the POR circuit from biasing up,

which can potentially cause an unpredicted state in the HG output.

The HG high-side driver circuit includes a latch. A signal from the POR block resets the latch, turning HG output

off. Without the POR signal, this latch may be indeterminate in its initial state upon powering up. The slew rate of

CB-SW voltage may affect the latch's initial state, as well as normal leakage paths through the transistors

controlling the latch.

Product Folder Links: LM2725 LM2726