Datasheet

PWM_IN
EN
Power
On
Reset
Shoot-through
Protection
V
CC
LG
GND
Logic
CBOOT
HG
SW
+4V ~ +7V
+
-
V
IN
(up to 35V)
V
OUT
Q
1
Q
2
Items in bold
are external
to the IC.
PFET
GND
8
LG
7
VCC
6
EN
5
PWM_IN
4
CBOOT 3
HG
2
SW
1
LM2725, LM2726
SNVS144D –NOVEMBER 2000–REVISED MARCH 2013 www.ti.com
Connection Diagram
8-Lead Small Outline Package
Figure 1. Top View
PIN DESCRIPTIONS
Pin Name Function
1 SW Top driver return. Should be connected to the common node of top and bottom FETs.
2 HG Top gate drive output.
3 CBOOT Bootstrap. Accepts a bootstrap voltage for powering the high-side driver.
4 PWM_IN Accepts a 5V-logic control signal.
5 EN Chip Enable. Active HIGH. Must be asserted during power up and down.
6 VCC Connect to +5V supply.
7 LG Bottom gate drive output.
8 GND Ground.
Block Diagram
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Product Folder Links: LM2725 LM2726