Datasheet

Battery or
Power
Source
L1
6.8PH
D
(Schottky)
C
OUT
10PF
R
FB2
10k
C
C
680pF
R
C
10k
1
4
3
5
6
7
2
FSLCT
FB
GND
V
IN
SW
12V
R
FB1
30.1k
L2
6.8PH
C
SEPIC
1PF
LM2698
SHDN
V
C
6.8V
C
IN
47PF
0.1PF
500
-5V,
400mA
LM2698
SNVS153E –MAY 2001–REVISED APRIL 2013 www.ti.com
C
IN
should be chosen using the same relationship as in the boost converter (see the C
IN
section). C
IN
must be
able to provide the necessary RMS current.
Figure 22. Level-Shifted SEPIC Converter
Level-Shifted SEPIC
The circuit shown in Figure 22 is similar to the SEPIC shown in Figure 21, except that it is level shifted to provide
a negative output voltage. This is achieved by connecting the ground of the LM2698 to the output. The circuit
analysis for the level-shifted SEPIC is the same as the SEPIC. The voltage at the input of the LM2698 will need
to be clamped if the absolute value of the output voltage plus the input voltage exceeds 12V, the absolute
maximum rating for the V
IN
pin. The simplest way to do this is with a zener diode, as shown in Figure 22.
Likewise, if the FSLCT pin is pulled high to operate at 1.25 MHz, its voltage must not exceed 12V. To prevent
any high frequency noise from entering the LM2698's internal circuitry, a high frequency bypass capacitor must
be placed as close to pin 6 as possible. A good choice for this capacitor is a 0.1µF ceramic capacitor.
Layout Consideration
The GND pin and the NC pin is recommended to be connected by a short trace as shown below.
Power Dissipation
The output power of the LM2698 is limited by its maximum power dissipation. The maximum power dissipation is
determined by the formula
P
D
= (T
jmax
- T
A
)/θ
JA
(26)
where T
jmax
is the maximum specified junction temperature (125°C), T
A
is the ambient temperature, and θ
JA
is
the thermal resistance of the package. θ
JA
is dependant on the layout of the board as shown below.
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