Datasheet

A
DC
=
118
*
R
LOAD(MIN)
R
DSON(MIN)
(1 - D
MAX
)
1 +
0.144 * f
S
L
V
IN
R
DSON(MIN)
 
+ 1 + D
MAX
(1 - D
MAX
)
3
R
LOAD(MIN)
2Lf
S
x
R
C
=
10 x A
DC
C
C1
Z
P1(max)
Z
P2
Z
RHP(MIN)
:
Z
z2
= 10 x Z
P1(max)
(rad/s),
=
A
DC
Z
P2
Z
RHP(MIN)
1
C
C1
R
C
Set Z
P2
= 2S(40)(rad/s)
(rad/s)
|
C
C1
R
OUT
1
Z
RHP(MIN)
=
R
LOAD(MIN)
(rad/s)
L
(
2
V
IN(MIN)
V
OUT
(
R
LOAD(MIN)
=
I
OUT(MAX)
V
OUT
C
OUT
R
LOAD(MIN)
1
Z
PI(MAX)
|
(rad/s)
LM2698
www.ti.com SNVS153E –MAY 2001–REVISED APRIL 2013
Quick Compensator Design
Calculate:
(14)
where,
(15)
(16)
(17)
where R
OUT
= 875kΩ
Choose C
C1
= 4.7nF
(18)
Choose
(19)
Where,
(20)
If the output capacitor is of high ESR (0.1Ω or higher), it may be necessary to use C
C2
. A rule of thumb is that if
1/(2πC
OUT
ESR) (Hz) is lower than f
S
/2 (Hz), C
C2
should be used. Choose C
C2
such that:
(R
C
+ R
OUT
)(C
OUT
ESR) / (R
C
R
OUT
) (F) (21)
where R
OUT
= output impedance of the error amp (875 kΩ).
Improving Transient Response Time
The above compensator design provides a loop gain with high phase margin for a large stability margin. The
transient response time of this loop is limited by the lower mid-frequency gain necessary to achieve a high phase
margin. If it is desired to increase the transient response time, C
C1
may be decreased. Decreasing C
C1
by 2x, 4x,
and 6x will yield increasingly shorter transient response times, however the loop phase margin will become
progressively lower as C
C1
is decreased. When optimizing the loop gain for transient response time, it is
recommended to keep the phase margin above 40°.
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