Datasheet

Efficiency =
Power_Out
Power_Out + Total_Power_Loss
1
2
'I
L
R
ESR
V
OUT
= V
L
= V
AVERAGE
- V
RIPPLE
= V
AVERAGE
-
1
2
LM2696
SNVS375B –OCTOBER 2005–REVISED APRIL 2013 www.ti.com
The output voltage is given by the following relationship:
(21)
as discussed in the FEEDBACK RESISTORS section of this document.
TRANSIENT RESPONSE
Constant on-time architectures have inherently excellent transient line and load response. This is because the
control loop is extremely fast. Any change in the line or load conditions will result in a nearly instantaneous
response in the PWM off time.
If one considers the switcher response to be nearly cycle-by-cycle, and amount of energy contained in a single
PWM pulse, there will be very little change in the output for a given change in the line or load.
EFFICIENCY
The constant on-time architecture features high efficiency even at light loads. The ability to achieve high
efficiency at light loads is due to the fact that the off-time will become necessarily long at light loads. Having
extended the off-time, there is little mechanism for loss during this interval.
The efficiency is easily estimated using the following relationships:
Power loss due to FET:
P
FET
= P
C
+ P
GC
+ P
SW
Where
• P
C
= D • (I
OUT
2
• R
DS_ON
)
• P
GC
= AV
IN
+ V
GS
• Q
GS
• f
SW
• P
SW
= 0.5 • V
IN
· I
OUT
• (t
r
+ t
f
) • f
SW
(22)
Typical values are:
R
DS_ON
= 130 mΩ
V
GS
= 4V
Q
GS
= 13.3 nC
t
r
= 3.8 ns
t
f
= 4.5 ns Power loss due to catch diode:
P
D
= (1-D) • (I
OUT
• V
f
) (23)
Power loss due to DCR and ESR:
P
DCR
= I
OUT
2
• R
DCR
(24)
P
ESR_OUTPUT
= I
RIPPLE
2
/√12 • R
ESR_OUTPUT
(25)
P
ESR_INPUT
= I
OUT
2
(D(1-D)) • R
ESR_INPUT
(26)
Power loss due to Controller:
P
CONT
= V
IN
• I
Q
(27)
I
Q
is typically 1.3 mA (28)
The efficiency may be calculated as shown below:
Total power loss = P
FET
+ P
D
+ P
DCR
+ P
ESR_OUTPUT
+ P
ESR_INPUT
+ P
CONT
(29)
Power Out = I
OUT
• V
OUT
(30)
(31)
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