Datasheet

Application Circuits (Continued)
OBTAINING OUTPUT VOLTAGES OF LESS THAN 1.25V
Some applications require output voltages less than 1.25V.
The circuit shown in Figure 5 will allow the LM2655 to do
such a conversion. By referencing the two feedback resis-
tors to V
ADJ
(V
ADJ
>
1.24V), V
OUT
can be adjusted from 0V
to V
ADJ
by the equation:
V
OUT
=(V
REF
-V
ADJ
)*(R
FB1
+R
FB2
)/R
FB2
+V
ADJ
where V
REF
= 1.24V. V
ADJ
can be any voltage higher than
V
REF
(1.24V). In Figure 5,V
ADJ
is produced by an LMV431
adjustable reference following the equation:
V
ADJ
= 1.24*(R
ADJ1
/R
ADJ2
+ 1).
Pcb Layout Considerations
Layout is critical to reduce noise and ensure specified per-
formance. The important guidelines are listed as follows:
1. Minimize the parasitic inductance in the loop of input
capacitors and the internal MOSFETs by connecting the
input capacitors to V
IN
and PGND pins with short and
wide traces. The high frequency ceramic bypass capaci-
tor, in particular, should be placed as close to and no
more than 5mm from the V
IN
pin. This is important
because the rapidly switching current, together with wir-
ing inductance can generate large voltage spikes that
may result in noise problems.
2. Minimize the trace from the center of the output resistor
divider to the FB pin and keep it away from noise
sources to avoid noise pick up. For applications that
require tight regulation at the output, a dedicated sense
trace (separated from the power trace) is recommended
to connect the top of the resistor divider to the output.
3. If the Schottky diode D is used, minimize the traces
connecting D to SW and PGND pins. Use short and wide
traces.
4. If the low-side MOSFET is used, minimize the trace
connecting the LDR pin to the gate of the MOSFET, and
the traces to SW and PGND pins. Use short and wide
traces for the power traces going from the MOSFET to
SW and PGND pins.
10128424
FIGURE 5. Obtaining output voltages of less than 1.25V
LM2655
www.national.com13