Datasheet

LM2650
www.ti.com SNVS133C –JUNE 1999–REVISED APRIL 2013
OPERATION
OVERVIEW
The LM2650 uses two step-down conversion modes: fixed-frquency pulse-width modulation (PWM) and
hysteretic. It moves freely and automatically between them, using PWM for moderate to heavy loads and
hysteretic for light loads.
For clarity, separate block diagrams for each conversion mode have been included. See Figure 15 and
Figure 16. Blocks used in both modes appear in both diagrams with the same label. For example, both modes
use the input buffer B. To keep the diagrams simple, most power supply rails have been omitted. R3, C10, R
C
,
C
C
, C
B
, L1, R1, R2, and C
OUT
are outside the IC.
THE PWM CIRCUIT (Figure 15)
The PWM is a fixed-frequency, voltage-mode pulse-width modulator. It consists of four functional blocks: an input
buffer, an error amplifier, a modulator, and a power stage.
1. The input buffer B: B is a voltage follower. A fraction of the output voltage is fed back to its noninverting input
FB. Circumventing B by using the COMP input as the feedback input will cause the IC to malfunction.
2. The error amplifier EA: EA is a voltage amplifier. It subtracts the feedback voltage from the 1.25V reference
and amplifies the difference to produce an error voltage for the control loop. For the purpose of loop
compensation, EA is typically configured as an integrator. In this configuration, a capacitor C
C
and a resistor
R
C
are connected in series between the inverting input COMP and the output terminal EA OUT. The
capacitor and the internal 6.5kΩ resistor create a pole, while the capacitor and series resistor create a zero.
3. The modulator: The modulator is the heart of the PWM circuit. It consists of the 90 kHz oscillator, the voltage
comparator C1, and output logic represented here as a simple SR latch.
– The modulator generates a continuous stream of rectangular, signal-level. It generates the pulses at a
fixed frequency, and it modulates or varies their widths in response to variations in the error voltage. The
pulses appear at Q, the output of the SR latch. An increase in the error voltage results in a proportional
increase in the pulse widths, and, conversely, a decrease in the error voltage results in a proportional
decrease in the pulse widths.
– The oscillator produces a 90 kHz sawtooth that ramps between 1V and 2V. At the beginning of each
ramp, the oscillator sets the SR latch sending Q high. As the ramp voltage surpasses the error voltage,
C1 resets the SR latch sending Q low. An increase in the error voltage increases the time between the
setting and the resetting of the SR latch which , in turn, results in an equal increase in pulse widths: that
is, an equal increase in the time Q spends high in each cycle. A decrease in the error voltage has the
opposite effect on the pulse widths as it decreases the time between the setting and resetting of the SR
latch.
4. The power stage: The power stage puts some punch between the output of the modulator by translating the
stream of signal-level pulses generated by the modulator into a stream of power pulses that swing from
ground up to the input voltage while sinking and sourcing as much as 3.5A. The power stage consists of two
gate drivers DH and DL, two linear voltage regulators VRegH and VRegL, and two NMOS power FETs Q1
and Q2.
– The power pulses appear at the SW mode. When Q goes high, DL drives the gate of Q2 low turning Q23
off. While Q2 turns off, the SW potential may remain at just below ground as the body diode of Q2
conducts what was previously reverse current (source-to-drain) in Q2, or the SW potential may swing up
to just above the input voltage as the body diode of Q1 conducts what was previously forward current
(drain-to-source) in Q2. About 50 ns after Q goes high, DH drives the gate of Q1 high turning Q1 on. If
the task remains, Q1 pulls the SW potential up, if not, Q1 simply takes over the conduction responsibility
from its own body diode. When Q goes low, the inverse action occurs resulting in the SW potential
swinging from the input voltage to the ground. The 50 ns delay between one switch beginning to turn off
and the other switch beginning to turn on prevents the switches from "shooting through" directly from the
input supply to the ground.
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