Datasheet

LM2650
www.ti.com SNVS133C –JUNE 1999–REVISED APRIL 2013
Electrical Characteristics (continued)
V
PVIN
= 15V, V
SLEEP LOGIC
= 0V and V
SD
= 0V unless superseded under Conditions. Typicals and limits appearing in plain type
apply for T
A
= T
J
= +25°C. Limits appearing in boldface type apply over the full junction temperature range shown under
Operating Ratings.
Symbol Parameter Conditions Typ
(1)
Limit
(2)
Units
I
QSD
Quiescent Current in Shutdown V
SD
= 3V
(5)
9 μA
mode 20/25 μA(max)
R
DS(on)
HS DC On-Resistance I
DS
= 1A, 130 mΩ
Drain-to-Source of the High-Side V
SLEEPLOGIC
= 3V, 170/245 mΩ(max)
Power Switch V
FB
= 3V,
V
BOOT
= 24V
R
DS(on)
LS DC On-Resistance I
DS
= 1A, 125 mΩ
Drain-to-Source of the Low-Side V
FB
= 3V 175/245 mΩ(max)
Power Switch
I
L HS
Leakage current of the High-Side V
PVIN
= 18V, V
SW
= 0V, 100 nA
10
Power Switch V
SD
= 3V μA(max)
I
L LS
Leakage current of the Low-Side V
PVIN
= 18V, V
SW
= 18V, 95 μA
210
Power Switch V
SD
= 3V μA(max)
I
LIMIT
Active Current Limit of the High- V
PVIN
= 15V, 5.5 A
Side Power Switch V
BOOT
= 24V, 3.5 A(min)
V
FB
= 3V, 7.5 A(max)
V
SLEEPLOGIC
= 3V,
F
OSC
Oscillator Frequency V
FB
= V
REF
−20 mV 90 kHz
80/75 kHz(min)
100/105 kHz(max)
F
MAX
Maximum Oscillator Frequency I
FREQ ADJ
= 100μA,
(6)
315 kHz
V
FB
= V
REF
−20 mV 270/260 kHz(min)
360/370 kHz(max)
D
MAX
Maximum Duty Cycle V
FB
= V
REF
−20 mV, 97 %
F
OSC
Not Adjusted 94/93 %(min)
D
MIN
Minimum Duty Cycle V
FB
= V
REF
+50 mV, 2.8 %
F
OSC
Not Adjusted 5 %(min)
V
DD
Internal Rail Voltage I
VDD
= 1 mA 4.0 V
3.6/3.4 V(min)
4.2/4.3 V(max)
V
BOOT
Bootstrap Regulator Voltage I
BOOT
= 1 mA 7.5 V
(VRegH) 6.5/6.0 V(min)
I
SS
Soft Start Current 10 μA
13.5/20.0 μA(max)
V
HYST
Hysteresis of the Sleep V
SLEEPLOGIC
= 3V 30 mV
Comparator (C2 Figure 16) 10 mV(min)
50 mV(max)
V
IL
of SD 0.95 V(max)
V
IH
of SD 2.10 V(min)
V
IL
of SLEEP LOGIC 0.9 V(max)
V
IH
of SLEEP LOGIC 2.0 V(min)
V
IL
of SYNC 0.50 V(max)
V
IH
of SYNC 1.45 V(min)
T
SD
T
J
for Thermal Shutdown 170 °C
(5) Quiescent current is the total current flowing into the P
VIN
and V
IN
pins. I
Q
includes the current used to drive the gates of the two NMOS
power FETs at the nominal switching frequency. I
QS
includes no such current.
(6) Pulling 100μA out of FREQ ADJ simulates adjusting the oscillator frequency with a 12.5 kΩ resistor connected from FREQ ADJ to GND.
The sleep mode cannot be used at switching frequencies above 250 kHz.
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