Datasheet
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LM26480
SNVS543I –JANUARY 2008–REVISED MAY 2013
www.ti.com
Connection Diagram
Figure 2. 24-Lead WQFN Package (top view)
Table 1. Default Options
Oscillator
Order Suffix Spec Buck Modes nPOR Delay UVLO Sync AECQ
Frequency
SQ-AA NOPB 2.0 MHz Auto-Mode 60 mS Enabled Disabled No
QSQ-AA NOPB 2.0 MHz Auto-Mode 60 mS Enabled Disabled Grade 1
QSQ-CF NOPB 2.1 MHz Forced PWM 60 mS Disabled Disabled Grade 1
SQ-BF NOPB 2.0 MHz Forced PWM 60 mS Enabled Enabled No
QSQ-8D NOPB 2.1 MHz Forced PWM 130 µS Enabled Disabled Grade 1
Table 2. PIN DESCRIPTIONS
(1)
WQFN Pin
Name I/O Type Description
No.
1 VINLDO12 I PWR Analog Power for Internal Functions (VREF, BIAS, I
2
C, Logic)
2 SYNC I G/(D) Frequency Synchronization pin which allows the user to connect an external clock
signal to synchronize the PMIC internal oscillator. Default OFF and must be
grounded when not used. Part number LM26480SQ-BF has this feature enabled.
Please contact Texas Instruments Sales Office/Distributors for availability of
LM26480SQ-BF.
3 NPOR O D nPOR Power on reset pin for both Buck1 and Buck 2. Open drain logic output 100K
pullup resistor. nPOR is pulled to ground when the voltages on these supplies are
not good. See Flexible Power-On Reset (i.e., Power Good with Delay) section for
more info.
4 GND_SW1 G G Buck1 NMOS Power Ground
5 SW1 O PWR Buck1 switcher output pin
6 VIN1 I PWR Power in from either DC source or Battery to Buck1
7 ENSW1 I D Enable Pin for Buck1 switcher, a logic HIGH enables Buck1. Pin cannot be left
floating.
8 FB1 I A Buck1 input feedback terminal
9 GND_C G G Non-switching core ground pin
10 AVDD I PWR Analog Power for Buck converters
11 FB2 I A Buck2 input feedback terminal
12 ENSW2 I D Enable Pin for Buck2 switcher, a logic HIGH enables Buck2. Pin cannot be left
floating.
13 VIN2 I PWR Power in from either DC source or Battery to Buck2
(1) A: Analog Pin D: Digital Pin G: Ground Pin PWR: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin
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