Datasheet

0402, 6.3V, X5R
0603, 10V, X5R
0 1.0 2.0 3.0 4.0 5.0
DC BIAS (V)
20%
40%
60%
80%
100%
CAP VALUE (% of NOMINAL 1 PF)
LM26480
SNVS543I –JANUARY 2008–REVISED MAY 2013 www.ti.com
As shown in the graph, increasing the DC bias condition can result in the capacitance value that falls below the
minimum value given in the recommended capacitor specifications table. Note that the graph shows the
capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended
that the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for all conditions,
as some capacitor sizes (e.g. 0402) may not be suitable in the actual application.
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a
temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R
has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic
capacitors, larger than 1 μF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance
can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over
Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47 μF to 4.7 μF range. Another
important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it
would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the
same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the
temperature goes from 25°C down to −40°C, so some guard band must be allowed.
Capacitor Min Value Unit Description Recommended Type
CLDO1 0.47 µF LDO1 output capacitor Ceramic, 6.3V, X5R
CLDO2 0.47 µF LDO2 output capacitor Ceramic, 6.3V, X5R
CSW1 10 µF SW1 output capacitor Ceramic, 6.3V, X5R
CSW2 10 µF SW2 output capacitor Ceramic, 6.3V, X5R
Analog Power Signal Routing
All power inputs should be tied to the main VDD source (i.e. battery), unless the user wishes to power it from
another source. (i.e. powering LDO from Buck output).
The analog VDD inputs power the internal bias and error amplifiers, so they should be tied to the main VDD. The
analog VDD inputs must have an input voltage between 2.8 and 5.5 V, as specified in the Electrical
Characteristics section of this datasheet.
The other Vins (VINLDO1, VINLDO2, VIN1, VIN2) can actually have inputs lower than 2.8V, as long as it's higher
than the programmed output (+0.3V, to be safe). The analog and digital grounds should be tied together outside
of the chip to reduce noise coupling.
For more information on board layout techniques, refer to Application Note AN–1187 “Leadless Lead frame
Package (LLP)” on http://www.ti.com This application note also discusses package handling, solder stencil and
the assembly process.
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