Datasheet

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LM26480 Hardware Block Description

As seen in Figure 5, R1 refers to the top resistor which corresponds to R2 and R4 for the bucks, and R6

and R8 for the LDOs. Similarly, R2 is the bottom resistor which corresponds to R3 and R5 for the bucks,

and R7 and R9 for the LDOs.

C1 corresponds to C3 and C9 top feedback caps for the bucks, and C2 refers to the bottom feedback

caps C4 and C10. For a more detailed diagram of the evaluation board, please refer to Section 11.

7 LM26480 Hardware Block Description

The LM26480 evaluation board is designed to allow the user to test the blocks independently as well as in

the system. Jumpers 1-6 as described in the Jumper table allow the VDD and GND path of each of the

blocks to be separated from the rest of the blocks.

To look at each of the blocks, follow the instructions below:

1. Start with all the jumpers connected.

2. Remove the connecting jumpers (JP3, JP6, JP9, or JP10) based on the jumper table to isolate the

power and ground planes of the block under test.

3. Connect a power supply (V

OUT

+ 0.3V) to the input of the desired block referenced to its corresponding

ground.

4. Enable the block and proceed with normal testing.

The output voltage of the low dropout regulators can be accessed at the ‘Turrets’ (LDO1 and LDO2)

referenced to GND_M. These are marked on the silkscreen of the evaluation board.

The output voltage of the two buck regulators can be accessed at the ‘Turrets’ BUCK1, BUCK2 referenced

to GND1, and GND2.

External power supplies can be attached to AVDD referenced to GND_C. The voltage supplied to the

system must be between the range of 2.8V to 5.5V.

Table 3. Jumper Settings

Jumper Purpose Note

JP 1,3,6,9,10 These jumpers connect different V

s to the JP3 and JP6 allow the bucks to be powered from the system

system VDD (AVDD): power.

JP1 connects VINLDO1 to AVDD JP9 and JP10 allow the LDOs to be powered from the system

JP3 connects VIN1 to AVDD power.

JP6 connects the VIN2 to AVDD JP1 powers the internal bias and error amplifiers from the

JP9 connects VINLDO1 to AVDDM system power. The voltage applied to AVDD and VINLDO12

JP10 connects VINLDO2 to AVDD should be in the range of 2.8 – 5.5V.

JP 4,5,7,8 These jumpers tie the enables of each When connected, these jumpers enable the regulators. If

regulator to VDD: disconnected, the regulator will power off.

JP4 - Buck1

JP5 - Buck2

JP7- LDO2

JP8 - LDO1

JP 2 This jumper connects the SYNC pin to GND. SYNC is default OFF. Please contact the Texas Instruments

Sales Office if you wish to use this feature.

SNVA329D–March 2008–Revised April 2013 AN-1800 Evaluation Kit for LM26480 - Dual DC/DC Buck Regulators with

Dual Low-Noise Linear Regulators

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