Datasheet
LM26400Y
SNVS457C –FEBRUARY 2007–REVISED APRIL 2013
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Connection Diagram
Figure 1. 16-Lead HTSSOP (top view) Figure 2. 16-Lead WSON (top view)
Package Drawing PWP0016A Package Drawing NHQ0016A
PIN DESCRIPTIONS
Pin Name Description
Feedback pin of Channel 1. Connect FB1 to an external voltage divider to set the output
1 FB1
voltage of Channel 1.
Soft start pin of Channel 1. Connect a capacitor between this pin and ground to program the
2 SS1
start up speed.
Enable control input for Channel 1. Logic high enables operation. Do not allow this pin to float
3 EN1
or be greater than V
IN
+ 0.3V.
Input supply for generating the internal bias used by the entire IC and for generating the
4 AVIN
internal bootstrap bias. Needs to be locally bypassed.
Signal and Power ground pin. Kelvin connect the lower resistor of the feedback voltage divider
5 GND
to this pin for good load regulation.
Enable control input for Channel 2. Logic high enables operation. Do not allow this pin to float
6 EN2
or be greater than V
IN
+ 0.3V.
Soft start pin of Channel 2. Connect a capacitor between this pin and ground to program the
7 SS2
start up speed.
Feedback pin of Channel 2. Connect FB2 to an external voltage divider to set the output
8 FB2
voltage of Channel 2.
Supply rail for the gate drive of Channel 2's NMOS switch. A bootstrap capacitor should be
9 BST2
placed between the BST2 and SW2 pins.
10 SW2 Switch node of Channel 2. Connects to the inductor, catch diode, and bootstrap capacitor.
Input voltage of the power supply. Directly connected to the drain of the internal NMOS switch.
11, 12, 13,14 PVIN
Tie these pins together and connect to a local bypass capacitor.
15 SW1 Switch node of Channel 1. Connects to the inductor, catch diode, and bootstrap capacitor.
Supply rail for the gate drive of Channel 1's NMOS switch. A bootstrap capacitor should be
16 BST1
placed between the BST1 and SW1 pins.
Must be connected to system ground for low thermal impedance and low grounding
DAP Die Attach Pad
inductance.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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