Datasheet
LM2623
SNVS188G –MAY 2004–REVISED DECEMBER 2005
www.ti.com
ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for T
J
= 25°C, and limits in boldface type apply over the full operating temperature range of
−40°C to +85°C. Unless otherwise specified: V
DD
= V
OUT
= 3.3V.
Symbol Parameter Condition Typ Min Max Units
V
DD_ST
Start-Up Supply Voltage 25°C I
LOAD
= 0mA
(1)
1.1 V
V
IN_OP
Minimum Operating Supply I
LOAD
= 0mA 0.65 .8 V
Voltage (once started)
V
FB
FB Pin Voltage 1.24 1.2028 1.2772 V
V
OUT_MAX
Maximum Output Voltage 14 V
η Efficiency V
IN
= 3.6V; V
OUT
= 5V; I
LOAD
=
87
500mA
%
V
IN
= 2.5V; V
OUT
= 3.3V; I
LOAD
=
87
200mA
D Switch Duty Cycle 17 %
I
DD
Operating Quiescent Current
(2)
FB Pin > 1.3V; EN Pin at V
DD
80 110 µA
I
SD
Shutdown Quiescent Current
(3)
V
DD
, BOOT and SW Pins at 5.0V; 0.01 2.5 µA
EN Pin <200mV
I
CL
Switch Peak Current Limit LM2623A 2. 85 2.2 A
I
C
Switch Peak Current Limit LM2623 1.2 A
R
DS_ON
MOSFET Switch On Resistance 0.17 0.26 Ω
θ
JA
Thermal Resistance DGK Package, Junction to 240 °C/W
Ambient
(4)
θ
JA
Thermal Resistance WSON Package, Junction to 40 °C/W
Ambient
(4) (5)
θ
JA
Thermal Resistance WSON Package, Junction to 56 °C/W
Ambient
(4) (6)
Enable Section
V
EN_LO
EN Pin Voltage Low
(7)
0.15V
DD
V
V
EN_HI
EN Pin Voltage High
(7)
0.7V
DD
V
(1) V
DD
tied to Boot and EN pins. Frequency pin tied to V
DD
through 121K resistor. V
DD_ST
= V
DD
when startu-up occurs. V
IN
is V
DD
+ D1
voltage (usually 10-50 mv at start-up)
(2) This is the current into the V
DD
pin.
(3) This is the total current into pins V
DD
, BOOT, SW and FREQ.
(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by T
jmax
(maximum junction temperature),
θ
JA
(junction to ambient thermal resistance), and T
A
(ambient temperature). The maximum allowable power dissipation at any
temperature is P
dmax
= (T
jmax
- T
A
)/ θ
JA
or the number given in the Absolute Maximum Ratings, whichever is lower.
(5) Junction to ambient thermal resistance (θ
JA
) is taken from a thermal modeling result, performed under the conditions and guidelines set
forthe in the JEDEC standard JESD51-17. The test board is a 4 layer FR-4 board measuring 102mm x 76mm x 1.6mm with a 3 x 2
array of thermal vias. The ground plane on the board is 50mm x 50 mm. Thickness of copper layers are 36mm/18mm/18mm/36mm
(1.5oz/10z/1oz/1.5ox). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W. (The DAP is soldered.) Fore more
information on WSON thermal topics, as well as WSON mounting and soldering specifications please refer to (SNOA401) Application
Note 1187 : Leadless Leadframe Package (LLP).
(6) Exposed DAP soldered to an exposed 1sq. inch area of 1 oz. copper. Thermal resistance can be decreased by using more copper are
to dissipate heat.
(7) When the EN pin is below V
EN_LO
, the regulator is shut down; when it is above V
EN_HI
, the regulator is operating.
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