Datasheet

Zc
(in rad/s)
2fs
nD'
#
A
DC(DB)
= 20log
10
{[(ZcLeff)// R
L
]//R
L
}
(in dB)
R
FB1
+ R
FB2
R
FB2
(
)
g
m
R
O
D'
R
DSON
f
PC2
=
1
2SC
C2
(R
C
//R
O
)
(in Hz)
f
ZC
=
1
2SC
C
R
C
(in Hz)
f
PC
=
1
2S(R
C
+ R
O
)C
C
(in Hz)
LM2622
www.ti.com SNVS068E –MAY 2000–REVISED MARCH 2013
SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components R
C
and C
C
is to set a dominant low frequency pole in
the control loop. Simply choose values for R
C
and C
C
within the ranges given in the INTRODUCTION TO
COMPENSATION section to set this pole in the area of 10Hz to 500Hz. The frequency of the pole created is
determined by the equation:
where
• R
O
is the output impedance of the error amplifier, approximately 1MegΩ (11)
Since R
C
is generally much less than R
O
, it does not have much effect on the above equation and can be
neglected until a value is chosen to set the zero f
ZC
. f
ZC
is created to cancel out the pole created by the output
capacitor, f
P1
. The output capacitor pole will shift with different load currents as shown by the equation, so setting
the zero is not exact. Determine the range of f
P1
over the expected loads and then set the zero f
ZC
to a point
approximately in the middle. The frequency of this zero is determined by:
(12)
Now R
C
can be chosen with the selected value for C
C
. Check to make sure that the pole f
PC
is still in the 10Hz to
500Hz range, change each value slightly if needed to ensure both component values are in the recommended
range. After checking the design at the end of this section, these values can be changed a little more to optimize
performance if desired. This is best done in the lab on a bench, checking the load step response with different
values until the ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should
produce a stable, high performance circuit. For improved transient response, higher values of R
C
should be
chosen. This will improve the overall bandwidth which makes the regulator respond more quickly to transients. If
more detail is required, or the most optimal performance is desired, refer to a more in depth discussion of
compensating current mode DC/DC switching regulators.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control
loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding
another capacitor, C
C2
, directly from the compensation pin V
C
to ground, in parallel with the series combination of
R
C
and C
C
. The pole should be placed at the same frequency as f
Z1
, the ESR zero. The equation for this pole
follows:
(13)
To ensure this equation is valid, and that C
C2
can be used without negatively impacting the effects of R
C
and C
C
,
f
PC2
must be greater than 10f
ZC
.
CHECKING THE DESIGN
The final step is to check the design. This is to ensure a bandwidth of ½ or less of the frequency of the RHP
zero. This is done by calculating the open-loop DC gain, A
DC
. After this value is known, you can calculate the
crossover visually by placing a −20dB/decade slope at each pole, and a +20dB/decade slope for each zero. The
point at which the gain plot crosses unity gain, or 0dB, is the crossover frequency. If the crossover frequency is
less than ½ the RHP zero, the phase margin should be high enough for stability. The phase margin can also be
improved by adding C
C2
as discussed earlier in the section. The equation for A
DC
is given below with additional
equations required for the calculation:
where
• R
L
is the minimum load resistance
• g
m
is the error amplifier transconductance found in the Electrical Characteristics table (14)
(15)
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