Datasheet
Psw
AC
= Vin x Iload x fsw x
Vin x 10
-9
1.33
©
§
¹
·
Vin
Vout
GND
SW
EP
GND
+
LM26003
SNVS576D –AUGUST 2008–REVISED MARCH 2013
www.ti.com
Figure 23. Example PCB Layout
It is a good practice to connect the EP, GND pin, and small signal components (COMP, FB, FREQ) to a separate
ground plane, shown in Figure 23 as EP GND, and in the schematics as a signal ground symbol. Both the
exposed pad and the GND pin must be connected to ground. This quieter plane should be connected to the high
current ground plane at a quiet location, preferably near the Vout ground as shown by the dashed line in
Figure 23.
The EP GND plane should be made as large as possible, since it is also used for thermal dissipation. Several
vias can be placed directly below the EP to increase heat flow to other layers when they are available. The
recommended via hole diameter is 0.3mm.
The trace from the FB pin to the resistor divider should be short and the entire feedback trace must be kept away
from the inductor and switch node. See Application Note AN-1229 SNVA054 for more information regarding PCB
layout for switching regulators.
Thermal Considerations and TSD
Although the LM26003 has a built in current limit, at ambient temperatures above 80°C, device temperature rise
may limit the actual maximum load current. Therefore, temperature rise must be taken into consideration to
determine the maximum allowable load current.
Temperature rise is a function of the power dissipation within the device. The following equations can be used to
calculate power dissipation (PD) and temperature rise, where total PD is the sum of FET switching losses, FET
DC losses, drive losses, Iq, and VBIAS losses:
PD
TOTAL
= Psw
AC
+ Psw
DC
+ PQG + P
Iq
+ P
VBIAS
(22)
(23)
Psw
DC
= D x Iload
2
x (0.095 + 0.00065 x (T
j
- 25)) (24)
P
QG
= Vin x 9.2 x 10
-9
x fsw (25)
P
Iq
= Vin x Iq (26)
P
VBIAS
= Vbias x I
VBIAS
(27)
Given this total power dissipation, junction temperature can be calculated as follows:
Tj = Ta + (PD
TOTAL
x θ
JA
) (28)
Where θ
JA
= 32°C/W (typically) when using a multi-layer board with a large copper plane area. θ
JA
varies with
board type and metallization area.
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