Datasheet

Exposed Pad
Connect to GND
COMP 8
VIN 1
VIN 2
VIN 3
AVIN 4
PGOOD 5
EN 6
SS 7
14 SYNC
15 VBIAS
16 VDD
17 BOOT
18 SW
19 SW
20 SW
AGND 10
FB 9
11 PGND
13 FPWM
12 FREQ
LM26003
SNVS576D AUGUST 2008REVISED MARCH 2013
www.ti.com
Connection Diagram
Figure 1. Top View
20-Lead TSSOP Package
PIN DESCRIPTIONS
Pin # Pin Name Description
1 VIN Power supply input for high side FET
2 VIN Power supply input for high side FET
3 VIN Power supply input for high side FET
4 AVIN Power supply input for IC supply
5 PGOOD Power Good pin. An open drain output which goes high when the output voltage is greater than 92% of nominal.
6 EN Enable is an analog level input pin. When pulled below 0.8V, the device enters shutdown mode.
7 SS Soft-start pin. Connect a capacitor from this pin to GND to set the soft-start time.
8 COMP Compensation pin. Connect to a resistor capacitor pair to compensate the control loop.
9 FB Feedback pin. Connect to a resistor divider between VOUT and GND to set output voltage.
10 AGND Analog GND as IC reference
11 PGND Power GND is GND for the switching stage of the regulator
12 FREQ Frequency adjust pin. Connect a resistor from this pin to GND to set the operating frequency.
13 FPWM FPWM is a logic level input pin. For normal operation, connect to GND. When pulled high, sleep mode operation
is disabled.
14 SYNC Frequency synchronization pin. Connect to an external clock signal for synchronized operation. SYNC must be
pulled low for non-synchronized operation.
15 VBIAS Connect to an external 3V or greater supply to bypass the internal regulator for improved efficiency. If not used,
VBIAS should be tied to GND.
16 VDD The output of the internal regulator. Bypass with a minimum 1.0 µF capacitor.
17 BOOT Bootstrap capacitor pin. Connect a 0.1 µF minimum ceramic capacitor from this pin to SW to generate the gate
drive bootstrap voltage.
18 SW Switch pin. The source of the internal N-channel switch.
19 SW Switch pin. The source of the internal N-channel switch.
20 SW Switch pin. The source of the internal N-channel switch.
EP EP Exposed Pad thermal connection. Connect to GND.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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