Datasheet

2 x S x R1 x C11

fzff =

Vfb

fpff =

fzff x Vout

LM26003

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SNVS576D –AUGUST 2008–REVISED MARCH 2013

A phase lead capacitor can also be added to increase the phase and gain margins. The phase lead capacitor is

most helpful for high input voltage applications or when synchronizing to a frequency greater than nominal. This

capacitor, shown as C11 in Figure 22, should be placed in parallel with the top feedback resistor, R1.

C11 introduces an additional zero and pole to the compensation network. These frequencies can be calculated

as shown below:

(21)

A phase lead capacitor will boost loop phase around the region of the zero frequency, fzff. fzff should be placed

somewhat below the fpz1 frequency set by C4. However, if C11 is too large, it will have no effect.

PCB Layout

Good board layout is critical for switching regulators such as the LM26003. First, the ground plane area must be

sufficient for thermal dissipation purposes, and second, appropriate guidelines must be followed to reduce the

effects of switching noise.

Switch mode converters are very fast switching devices. In such devices, the rapid increase of input current

combined with parasitic trace inductance generates unwanted Ldi/dt noise spikes at the SW node and also at the

VIN node. The magnitude of this noise tends to increase as the output current increases. This parasitic spike

noise may turn into electromagnetic interference (EMI) and can also cause problems in device performance.

Therefore, care must be taken in layout to minimize the effect of this switching noise.

The current sensing circuit in current mode devices can be easily affected by switching noise. This noise can

cause duty-cycle jitter which leads to increased spectrum noise. Although the LM26003 has 150 ns blanking time

at the beginning of every cycle to ignore this noise, some noise may remain after the blanking time. Following the

important guidelines below will help minimize switching noise and its effect on current sensing.

The switch node area should be as small as possible. The catch diode, input capacitors, and output capacitors

should be grounded to the same local ground, with the bulk input capacitor grounded as close as possible to the

catch diode anode. Additionally, the ground area between the catch diode and bulk input capacitor is very noisy

and should be somewhat isolated from the rest of the ground plane.

A ceramic input capacitor must be connected as close as possible to the AVIN pin as well as PVIN pin. The

capacitor between AVIN and ground should be grounded close to the GND pins of the LM26003 and the PVIN

capacitor should be grounded close to the Schottky diode ground. Often, the AVIN bypass capacitor is most

easily located on the bottom side of the PCB. It increases trace inductance due to the vias, it reduces trace

length however.

The above layout recommendations are illustrated below in Figure 23.

Product Folder Links: LM26003