Datasheet

Vout

20 mV/Div

2V/Div

100 mA/Div

4 Ps/DIV

LM26003

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SNVS576D –AUGUST 2008–REVISED MARCH 2013

VBIAS

The VBIAS pin is used to bypass the internal regulator which provides the bias voltage to the LM26003. When

the VBIAS pin is connected to a voltage greater than 3V, the internal regulator automatically switches over to the

VBIAS input. This reduces the current into VIN (Iq) and increases system efficiency. Using the VBIAS pin has the

added benefit of reducing power dissipation within the device.

For most applications where 3V < Vout < 10V, VBIAS can be connected to VOUT. If not used, VBIAS should be

tied to GND.

If VBIAS drops below 2.9V (typical), the device automatically switches over to supply the internal bias voltage

from Vin.

When the LM26003 is powered with the circuit's output voltage through VBIAS, especially at low output voltages

such as 3.3V, output ripple noise can couple in through the Vbias pin causing some falling edge jitter on the

switch node. To avoid this, additional bypassing close to the VBIAS pin with a low ESR capacitor can be

implemented. The circuit diagram in Figure 19 shows this bypass capacitor C8.

LOW VIN OPERATION AND UVLO

The LM26003 is designed to remain operational during short line transients when the input voltage may drop as

low as 3.0V. Minimum nominal operating input voltage is 4.0V. Below this voltage, switch R

DS(ON)

increases, due

to the lower gate drive voltage from VDD. The minimum voltage required at VDD is approximately 3.5V for

normal operation within specification.

VDD can also be used as a pull-up voltage for functions such as PGOOD and FPWM. Note that if VDD is used

externally, the pin is not recommended for loads greater than 1 mA.

If the input voltage approaches the nominal output voltage, the duty-cycle is maximized to hold up the output

voltage. In this mode of operation, once the duty-cycle reaches its maximum, the LM26003 can skip a maximum

of seven off pulses, effectively increasing the duty-cycle and thus minimizing the dropout from input to output.

Typical off-pulse skipping waveforms are shown in Figure 18.

Figure 18. Off-Pulse Skipping Waveforms Vin = 3.5V, Vnom = 3.3V, fnom = 305 kHz

UVLO is sensed at both VIN and VDD, and is activated when either voltage falls below 2.96V (typical). Although

VDD is typically less than 200 mV below VIN, it will not discharge through VIN. Therefore when the VIN voltage

drops rapidly, VDD may remain high, especially in sleep mode. For fast line voltage transients, using a larger

capacitor at the VDD pin can help to hold off a UVLO shutdown by extending the VDD discharge time. By

holding up VDD, a larger cap can also reduce the R

DS(ON)

(and dropout voltage) in low VIN conditions.

Alternately, under heavy loading the VDD voltage can fall several hundred mV below VIN. In this case, UVLO

may be triggered by VDD even though the VIN voltage is above the UVLO threshold.

When UVLO is activated the LM26003 enters a standby state in which VDD remains charged. As input voltage

and VDD voltage rise above 3.99V (typical) the device will restart from soft-start mode.

Product Folder Links: LM26003